Technique for semiconductor manufacturing

Patent metadata

Field	Value
Publication number	US-12198939-B2
Application number	US-202217808659-A
Country	US
Kind code	B2
Filing date	Jun 24, 2022
Priority date	Jul 16, 2020
Publication date	Jan 14, 2025
Grant date	Jan 14, 2025

Abstract

A technique for semiconductor manufacturing is provided. The technique includes the operations as follows. A semiconductor structure having a first material is received. A plurality of first main etches are performed to the semiconductor structure for a plurality of first durations under the first etching chemistry. A plurality of pumping operations are performed for a plurality of pumping durations, each of the pumping operations being prior to each of the first main etches. Each of the first durations is in a range of from about 1 second to about 2.5 seconds.

First claim

What is claimed is:

1. A technique for semiconductor manufacturing, comprising:
receiving a semiconductor structure having a first material and a second material;
performing a plurality of first main etches to the semiconductor structure for a plurality of first durations under a first etching chemistry;
performing a plurality of second main etches to the semiconductor structure for a plurality of second durations under a second etching chemistry, wherein the first material includes a first incubation time and the second material includes a second incubation time greater than the first incubation time under the first etching chemistry, wherein the first material includes a third incubation time and the second material includes a fourth incubation time less than the third incubation time under the second etching chemistry; and
performing a plurality of pumping operations for a plurality of pumping durations, each of the pumping operations being prior to each of the first main etches.

2. The technique of claim 1 , further comprising performing a plurality of pretreatments to the semiconductor structure, each of the pretreatments being prior to each of the first main etches.

3. The technique of claim 2 , wherein the pretreatments comprises one of a surface cleaning operation, a passivation operation, or a catalyzing operation.

4. The technique of claim 1 , wherein each of the pumping durations is in a range of from about 5 seconds to about 60 seconds.

5. The technique of claim 1 , further comprising performing a third main etch to the semiconductor structure for a third duration under the first etching chemistry subsequent to performing the first main etches.

6. The technique of claim 5 , wherein the third duration is greater than the first incubation time.

7. The technique of claim 1 , wherein each of the first durations is less than 3 seconds.

8. A technique for semiconductor manufacturing, comprising:
receiving a semiconductor structure having a first material and a second material, the first material having a first incubation time to a first etching chemistry, the second material having a second incubation time to the first etching chemistry, wherein the first incubation time is shorter than the second incubation time;
performing a plurality of first main etches to the semiconductor structure for a plurality of first durations under the first etching chemistry;
performing a second main etch to the semiconductor structure for a second duration under the first etching chemistry, wherein the second duration is different from the first duration;
performing a plurality of third main etches to the semiconductor structure for a plurality of third durations under a second etching chemistry, the first material having a third incubation time to the second etching chemistry, the second material having a fourth incubation time to the second etching chemistry, wherein the fourth incubation time is shorter than the third incubation time; and
performing a plurality of pretreatments to the semiconductor structure.

9. The technique of claim 8 , wherein each of the first durations is greater than the first incubation time and shorter than the second incubation time.

10. The technique of claim 8 , wherein each of the pretreatments being performed prior to each of the first main etches.

11. The technique of claim 8 , each of the pretreatments comprises applying HF, NH 3 , F 2 , NF 3 , H 2 O, H 2 , CH 4 , Cl 2 , SiCl 4 , FCl 3 , CH 3 F, O 2 , BCl 3 , or N 2 .

12. The technique of claim 8 , wherein the second duration is greater than the first incubation time and shorter than the second incubation time.

13. The technique of claim 8 , wherein the second duration is less than about 3.0 seconds.

14. The technique of claim 8 , wherein each of the first durations is less than about 3.0 seconds.

15. The technique of claim 8 , wherein the second material serves as an etch stop material to the first etching chemistry during each of the first main etches.

16. The technique of claim 8 , wherein an etching pressure of performing the first main etches is greater than about 10 Torr.

17. A technique for semiconductor manufacturing, comprising:
receiving a semiconductor structure having a first material and a second material, the first material having a first incubation time and the second material having a second incubation time greater than the first incubation time under a first etching chemistry, the first material having a third incubation time and the second material having a fourth incubation time less than the third incubation time under a second etching chemistry;
performing a first main etch to the semiconductor structure for a duration by the first etching chemistry; and
performing a second main etch to the semiconductor structure for the duration by the second etching chemistry.

18. The technique of claim 17 , wherein the duration is greater than the first incubation time and the third incubation time.

19. The technique of claim 18 , wherein the duration is shorter than the second incubation time and the fourth incubation time.

20. The technique of claim 17 , wherein an etching pressure of performing the first main etch or performing the second main etch is greater than about 10 Torr.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Han-Yu
• Lin Li-Te
• Lin Tze-Chung
• Lee Fang-Wei
• Chen Yi-Lun
• Chang Jung-Hao
• Lo Yi-Chen
• Lin Fo-Ju
• Sano Kenichi
• Lin Pinyen

Classifications

• H10P50/242 Primary

  of Group IV materials · CPC title

• H10P50/283 Primary

  by chemical means · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10D84/0151

  Manufacturing their isolation regions · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title