In-memory computing unit and in-memory computing circuit having reconfigurable logic

Patent metadata

Field	Value
Publication number	US-12198746-B2
Application number	US-202217966476-A
Country	US
Kind code	B2
Filing date	Oct 14, 2022
Priority date	Dec 2, 2021
Publication date	Jan 14, 2025
Grant date	Jan 14, 2025

Abstract

An in-memory computing circuit having reconfigurable logic, including: an input stage and N output stages which are cascaded. The input stage includes 2 N STT-MTJs. Each output stage includes STT-MTJs, of which a quantity is equal to a half of a quantity of STT-MTJs in a just previous stage. Two STT-MTJs in the previous stage and one STT-MTJ in the subsequent stage form a double-input single-output in-memory computing unit. Each double-input single-output in-memory computing unit can implement the four logical operations, i.e., NAND, NOR, AND, and OR, under different configurations. Data storage and logical operations can be realized under the same circuit architecture, and reconfigurations among different logic can be achieved.

First claim

The invention claimed is:

1. A double-input single-output (DISO) in-memory computing unit, comprising a first input spin transfer torque magnetic tunnel junction (STT-MTJ), a second input STT-MTJ, and one output STT-MTJ, wherein:
a first terminal of the first input STT-MTJ and a first terminal of the second input STT-MTJ are electrically connected and are configured to receive a first voltage;
a first terminal of the output STT-MTJ is configured to receive a second voltage;
a second terminal of the first input STT-MTJ and a second terminal of the second input STT-MTJ are electrically connected to a second terminal of the output STT-MTJ; and
a difference of first voltage with respect to the second voltage is an operating voltage of the DISO in-memory computing unit.

2. The DISO in-memory computing unit according to claim 1 , wherein:
each of the first input STT-MTJ, the second input STT-MTJ, and the output STT-MTJ comprises a free layer and a reference layer; and
the first terminal and the second terminal correspond to the free layer and the reference layer, respectively, for each of the first input STT-MTJ, the second input STT-MTJ, and the output STT-MTJ; or
the first terminal and the second terminal correspond to the reference layer and the free layer, respectively, for each of the first input STT-MTJ, the second input STT-MTJ, and the output STT-MTJ.

3. The DISO in-memory computing unit according to claim 1 , wherein:
the DISO in-memory computing unit is capable to implement different logic operations based on a change in configurations of the DISO in-memory computing unit;
each of the different logic operations is one of: NAND, NOR, AND, and OR; and
the configurations comprises a logic level to which the output STT-MTJ is initialized, the operating voltage, and a ratio among critical dimensions of the first input STT-MTJ, the second input STT-MTJ, and the output STT-MTJ.

4. The DISO in-memory computing unit according to claim 3 , wherein the DISO in-memory computing unit is configured to implement:
the NAND logical operation, in response to the logic level being a first level, the operating voltage being in a first range, and the ratio being the first ratio;
the NOR logical operation, in response to the logic level being the first level, the operating voltage being in a second range, and the ratio being the first ratio;
the AND logical operation, in response to the logic level being the second level, the operating voltage being in a third range, and the ratio being a second ratio; and
the NOR logical operation, in response to the logic level being the second level, the operating voltage being in a fourth range, and the ratio being a third ratio.

5. The DISO in-memory computing unit according to claim 3 , wherein:
the first level is logic 0, and the second level is logic 1;
the first range is 0.0731V to 0.0908V, the second range is 0.0650V to 0.0730V, the third range is −0.202V to 0.195V, and the fourth range is −0.211V to 0.205V; and
the first ratio is 1:1:1, the second ratio is 1:1:0.5, and the third ratio is 1:1:0.7.

6. An in-memory computing circuit having reconfigurable logic, comprising a plurality of DISO in-memory computing units, each of which is the DISO in-memory computing unit according to claim 1 , wherein the plurality of DISO in-memory computing units comprises:
(N+1) stages that are cascaded, wherein N is a positive integer, and for each i which is a positive integer smaller or equal to N:
a quantity of STT-MTJs in the (i+1)-th stage is equal to a half of STT-MTJs in the i-th stage;
the STT-MTJs in the (i+1)-th stage and STT-MTJ pairs in the i-th stage are in a one-to-one correspondence, and each of the STT-MTJ pairs comprises two STT-MTJs in the i-th stage; and
each STT-MTJ in the (i+1)-th stage and the corresponding two STT-MTJs in the i-th stage are comprised in one of the DISO in-memory computing units, wherein said STT-MTJ in the (i+1)-th stage serves as the output STT-MTJ, and the two STT-MTJs in the i-th stage serve as the first input STT-MTJ and the second input STT-MTJ.

7. The in-memory computing circuit according to claim 6 , further comprising a plurality of switches, configured to:
connect adjacent stages in the (N+1) stages; and
connect one or more stages in the (N+1) stages to a source supplying the operating voltage.

8. The in-memory computing circuit according to claim 6 , wherein:
each of the first input STT-MTJ, the second input STT-MTJ, and the output STT-MTJ comprises a free layer and a reference layer; and
the first terminal and the second terminal correspond to the free layer and the reference layer, respectively, for each of the first input STT-MTJ, the second input STT-MTJ, and the output STT-MTJ; or
the first terminal and the second terminal correspond to the reference layer and the free layer, respectively, for each of the first input STT-MTJ, the second input STT-MTJ, and the output STT-MTJ.

9. The in-memory computing circuit according to claim 8 , wherein:
each DISO in-memory computing unit in the in-memory computing circuit is capable to implement different logic operations based on a change in configurations of the DISO in-memory computing unit;
each of the different logic operations is one of: NAND, NOR, AND, and OR; and
the configurations comprises a logic level to which the output STT-MTJ is initialized, the operating voltage, and a ratio among critical dimensions of the first input STT-MTJ, the second input STT-MTJ, and the output STT-MTJ.

10. The in-memory computing circuit according to claim 9 , wherein each DISO in-memory computing unit in the in-memory computing circuit is configured to implement:
the NAND logical operation, in response to the logic level being a first level, the operating voltage being in a first range, and the ratio being the first ratio;
the NOR logical operation, in response to the logic level being the first level, the operating voltage being in a second range, and the ratio being the first ratio;
the AND logical operation, in response to the logic level being the second level, the operating voltage being in a third range, and the ratio being a second ratio; and
the NOR logical operation, in response to the logic level being the second level, the operating voltage being in a fourth range, and the ratio being a third ratio.

11. The in-memory computing circuit according to claim 10 , wherein:
the first level is logic 0, and the second level is logic 1;
the first range is 0.0731V to 0.0908V, the second range is 0.0650V to 0.0730V, the third range is −0.202V to 0.195V, and the fourth range is −0.211V to 0.205V; and
the first ratio is 1:1:1, the second ratio is 1:1:0.5, and the third ratio is 1:1:0.7.

12. The in-memory computing circuit according to claim 9 , wherein each DISO in-memory computing unit in the in-memory computing circuit is capable to implement each of NAND, NOR, AND, and OR logic operations.

13. The in-memory computing circuit according to claim 7 , wherein each of the plurality of switches is a single-pole single-throw electronic switch or a single-pole double-throw electronic switch.

14. The in-memory computing circuit according to claim 7 , wherein:
N is equal to 3, and the (N+1) stages comprises a first stage, a second stage, a third stage, and a fourth stage that are cascaded in the above-listed sequence;
the plurality of in-memory computing units comprises a first in-memory computing unit, a second in-memory computing unit, a third in-memory computing unit, a fourth in-memory computing unit, a fifth in-memory computing unit, a sixth in-memory computing unit, and a seventh in-memory comp

Assignees

• Inst Of Microelectronics Cas

Inventors

• Cui Yan
• Luo Jun
• Yang Meiyin
• Xu Jing

Classifications

• H03K19/20 Primary

  characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) · CPC title

• G11C11/1659

  Cell access · CPC title

• G11C11/54

  using elements simulating biological cells, e.g. neuron · CPC title

• H03K19/18

  using galvano-magnetic devices, e.g. Hall-effect devices · CPC title

• H03K19/1776

  for memories · CPC title