Array substrate and display device

Patent metadata

Field	Value
Publication number	US-12198599-B2
Application number	US-202318494796-A
Country	US
Kind code	B2
Filing date	Oct 26, 2023
Priority date	Feb 4, 2021
Publication date	Jan 14, 2025
Grant date	Jan 14, 2025

Abstract

The present disclosure relates to an array substrate and a display device. The array substrate includes a plurality of pixel units arranged in an array, each of the pixel units including a plurality of sub-pixels. The array substrate includes: a plurality of power lines which are arranged in a conductive layer on a base substrate, are arranged at intervals along a first direction and extend along a second direction, and are used for providing power signals to the sub-pixels; and a plurality of power leads which are arranged in another conductive layer, are arranged at intervals along the second direction and extend along the first direction. Projections of at least one of the power lines and at least one of the power leads on the base substrate intersect, and the projections of the power lines and the power leads on the base substrate form a grid-like structure.

First claim

What is claimed is:

1. An array substrate comprising a plurality of pixel units arranged in an array, each of the pixel units comprising a plurality of sub-pixels, wherein the array substrate comprises:
a plurality of power lines which are arranged in a conductive layer on a base substrate, are arranged at intervals along a first direction and extend along a second direction, and are used for providing power signals to the sub-pixels; and
a plurality of power leads which are arranged in another conductive layer, are arranged at intervals along the second direction and extend along the first direction;
wherein projections of at least one of the power lines and at least one of the power leads on the base substrate intersect, and the at least one of the power lines and the at least one of the power leads are connected through a via hole, and projections of the power lines and the power leads on the base substrate form a grid-like structure.

2. The array substrate according to claim 1 , wherein the array substrate comprises the base substrate and a first gate line layer, a second gate line layer, a source and drain layer and an anode layer which are stacked on the base substrate in sequence, the first direction is a row direction, and the second direction is a column direction;
wherein the plurality of power lines are arranged in the source and drain layer; and
wherein the plurality of power leads are arranged in the second gate line layer.

3. The array substrate according to claim 2 , wherein the array substrate further comprises:
a plurality of initialization signal lines which are arranged in the second gate line layer, extend along the first direction and are arranged at intervals along the second direction, and are used to provide initialization signals to the sub-pixels;
wherein each of the sub-pixels comprises a sub-pixel driving circuit, and the sub-pixel driving circuit comprises a capacitor comprising a first electrode plate and a second electrode plate, the first electrode plate is arranged in the first gate line layer, and the second electrode plate is arranged in the second gate line layer;
wherein a projection of each of the power leads on the base substrate is located between a projection of a corresponding initialization signal line among the plurality of initialization signal lines on the base substrate and a projection of the second electrode plate on the base substrate.

4. The array substrate according to claim 3 , wherein the array substrate further comprises:
a plurality of connection lines which are arranged in the source and dray layer or the anode layer, extend along the second direction and are arranged at intervals along the first direction;
wherein projections of at least one of the initialization signal lines and at least one of the connection lines on the base substrate intersect, and the at least one of the initialization signal lines and the at least one of the connection lines are connected through a via hole, so that the projections of the initialization signal lines and the connection lines on the substrate form a grid-like structure.

5. The array substrate according to claim 4 , further comprises:
a plurality of scan lines which are arranged in the first gate line layer, extend along the row direction and are arranged at intervals along the column direction, and are used providing scan signals to the sub-pixels; and
a plurality of reset signal lines which are arranged in the first gate line layer, extend along the row direction and are arranged at intervals along the column direction, and are used for providing reset signals to the sub-pixels.

6. The array substrate according to claim 5 , wherein in each sub-pixel area, a projection of a corresponding initialization signal line among the plurality of initialization signal lines on the base substrate is located between a projection of a corresponding reset signal line among the plurality of the plurality of reset signal lines and a projection of a scan line for a previous-stage sub-pixel, and the projection of the corresponding initialization signal line, the projection of the corresponding reset signal line and the projection of the scan line do not overlap with each other.

7. The array substrate according to claim 5 , wherein in each sub-pixel area, a projection of a corresponding initialization signal line among the plurality of initialization signal lines on the base substrate is located at a side of a projection of a corresponding reset signal line among the plurality of the plurality of reset signal lines away from a scan line for a previous-stage sub-pixel, and the projection of the corresponding initialization signal line, the projection of the corresponding reset signal line and the projection of the scan line do not overlap with each other.

8. The array substrate according to claim 5 , wherein:
in each sub-pixel area, a corresponding reset signal line among the plurality of reset signal lines and a scan line for a previous-stage sub-pixel are connected integrally; and
a projection of a corresponding initialization signal line among the plurality of initialization signal lines on the base substrate intersects with a projection of the corresponding reset signal line.

9. The array substrate according to claim 8 , wherein each of the initialization signal lines comprises a plurality of signal segments separated from each other, and the signal segments corresponds to the pixel units one to one;
wherein a projection of each of the signal segments has no overlap with a projection of a corresponding reset signal line in at least one of sub-pixel areas in a corresponding pixel unit, and the projection of each of the signal segments intersects with a projection of the corresponding reset signal line in a remaining sub-pixel area in the corresponding pixel unit.

10. The array substrate according to claim 4 , wherein the number of the connection lines is equal to the number of sub-pixels in the row direction, and in the row direction, the initialization signal lines and the connection lines are electrically connected through via holes in individual sub-pixel areas;
or, the number of the connection lines is smaller than the number of sub-pixels in the row direction, and in the row direction, the initialization signal lines and the connection lines are electrically connected through via holes in a part of sub-pixel areas.

11. The array substrate according to claim 10 , further comprising:
a plurality of data lines which are arranged in the source and drain layer, extend along the column direction and are arranged at intervals along the row direction, and are used for providing data signals to the sub-pixels.

12. The array substrate according to claim 11 , wherein each of the sub-pixels comprises an anode, the connection lines and the anode are both arranged in the anode layer, and the connection lines are insulated from the anode.

13. The array substrate according to claim 12 , further comprising:
a plurality of first conductive connection portions which are arranged in the source and drain layer, and are distributed in sub-pixel areas where projections of the initialization signal lines and the connection lines intersect;
wherein in a sub-pixel area where a first conductive connection portion among the plurality of first conductive connection portions is distributed, a projection of the first conductive connection portion on the base substrate has an overlapping area with a corresponding initialization signal line and a corresponding connection line, respectively, and the first conductive connection portion is connected to the corresponding connection line through a

Assignees

• Boe Technology Group Co Ltd

Inventors

• Han Long
• Liu Libin
• Huangfu Lujiang

Classifications

• G09G2320/066

  for control of contrast · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2310/0202

  Addressing of scan or signal lines · CPC title

• G09G2300/0819

  used for counteracting undesired variations, e.g. feedback or autozeroing · CPC title

• G09G2300/0465

  Improved aperture ratio, e.g. by size reduction of the pixel circuit, e.g. for improving the pixel density or the maximum displayable luminance or brightness · CPC title