Array substrate and display device

Patent metadata

Field	Value
Publication number	US-11837142-B2
Application number	US-202117638836-A
Country	US
Kind code	B2
Filing date	Feb 4, 2021
Priority date	Feb 4, 2021
Publication date	Dec 5, 2023
Grant date	Dec 5, 2023

Abstract

The present disclosure relates to an array substrate and a display device. The array substrate includes a plurality of initialization signal lines and a plurality of connection lines. The initialization signal lines are arranged in a conductive layer, extend along a first direction and are arranged at intervals along a second direction, and are used to provide initialization signals to the sub-pixels. The connection lines are arranged in another conductive layer, extend along the second direction and are arranged at intervals along the first direction. Projections of at least one initialization signal line and at least one connection line on the base substrate intersect, and the at least one initialization signal line and the at least one connection line are connected through a via hole, so that the projections of the initialization signal lines and the connection lines on the substrate form a grid-like structure.

First claim

What is claimed is:

1. An array substrate, comprising:
a plurality of pixel units arranged in an array, each of the pixel units comprising a plurality of sub-pixels, wherein the array substrate comprises:
a plurality of initialization signal lines which are arranged in a conductive layer on a base substrate, extend along a first direction and are arranged at intervals along a second direction, and are used to provide initialization signals to the sub-pixels, wherein the first direction intersects with the second direction; and
a plurality of connection lines which are arranged in another conductive layer on the base substrate, extend along the second direction and are arranged at intervals along the first direction, wherein;
projections of at least one of the initialization signal lines and at least one of the connection lines on the base substrate intersect, and the at least one of the initialization signal lines and the at least one of the connection lines are connected through a via hole, so that the projections of the initialization signal lines and the connection lines on the substrate form a grid-like structure;
the array substrate comprises the base substrate and a first gate line layer, a second gate line layer, a source and drain layer, and an anode layer which are stacked on the base substrate in sequence, the first direction is a row direction, and the second direction is a column direction;
the plurality of initialization signal lines are arranged in the second gate layer; and
the plurality of connection lines are arranged in the source and drain layer or the anode layer.

2. The array substrate according to claim 1 , further comprises:
a plurality of scan lines which are arranged in the first gate line layer, extend along the row direction and are arranged at intervals along the column direction, and are used providing scan signals to the sub-pixels; and
a plurality of reset signal lines which are arranged in the first gate line layer, extend along the row direction and are arranged at intervals along the column direction, and are used for providing reset signals to the sub-pixels.

3. The array substrate according to claim 2 , wherein in each sub-pixel area, a projection of a corresponding initialization signal line among the plurality of initialization signal lines on the base substrate is located between a projection of a corresponding reset signal line among the plurality of the plurality of reset signal lines and a projection of a scan line for a previous-stage sub-pixel, and the projection of the corresponding initialization signal line, the projection of the corresponding reset signal line and the projection of the scan line do not overlap with each other.

4. The array substrate according to claim 2 , wherein in each sub-pixel area, a projection of a corresponding initialization signal line among the plurality of initialization signal lines on the base substrate is located at a side of a projection of a corresponding reset signal line among the plurality of the plurality of reset signal lines away from a scan line for a previous-stage sub-pixel, and the projection of the corresponding initialization signal line, the projection of the corresponding reset signal line and the projection of the scan line do not overlap with each other.

5. The array substrate according to claim 2 , wherein:
in each sub-pixel area, a corresponding reset signal line among the plurality of reset signal lines and a scan line for a previous-stage sub-pixel are connected integrally; and
a projection of a corresponding initialization signal line among the plurality of initialization signal lines on the base substrate intersects with a projection of the corresponding reset signal line.

6. The array substrate according to claim 5 , wherein each of the initialization signal lines comprises a plurality of signal segments separated from each other, and the signal segments corresponds to the pixel units one to one;
wherein a projection of each of the signal segments has no overlap with a projection of a corresponding reset signal line in at least one of sub-pixel areas in a corresponding pixel unit, and the projection of each of the signal segments intersects with a projection of the corresponding reset signal line in a remaining sub-pixel area in the corresponding pixel unit.

7. The array substrate according to claim 1 , wherein the number of the connection lines is equal to the number of sub-pixels in the row direction, and in the row direction, the initialization signal lines and the connection lines are electrically connected through via holes in individual sub-pixel areas;
or, the number of the connection lines is smaller than the number of sub-pixels in the row direction, and in the row direction, the initialization signal lines and the connection lines are electrically connected through via holes in a part of sub-pixel areas.

8. The array substrate according to claim 7 , further comprising:
a plurality of power lines which are arranged in the source and drain layer, extend along the column direction and arranged at intervals along the row direction, and are used for providing power signals to the sub-pixels; and
a plurality of data lines which are arranged in the source and drain layer, extend along the column direction and are arranged at intervals along the row direction, and are used for providing data signals to the sub-pixels.

9. The array substrate according to claim 8 , wherein each of the sub-pixels comprises an anode, the connection lines and the anode are both arranged in the anode layer, and the connection lines are insulated from the anode.

10. The array substrate according to claim 9 , further comprising:
a plurality of first conductive connection portions which are arranged in the source and drain layer, and are distributed in sub-pixel areas where projections of the initialization signal lines and the connection lines intersect;
wherein in a sub-pixel area where a first conductive connection portion among the plurality of first conductive connection portions is distributed, a projection of the first conductive connection portion on the base substrate has an overlapping area with a corresponding initialization signal line and a corresponding connection line, respectively, and the first conductive connection portion is connected to the corresponding connection line through a via hole.

11. The array substrate according to claim 8 , wherein:
the connection lines are arranged in the source and drain layer;
in each sub-pixel area, a corresponding initialization signal line of the plurality of initialization signal lines comprises a main body section and an extension section which are connected to each other, the main body section of the corresponding initialization signal line extends along the row direction, and the extension section of the corresponding initialization signal line extends in a direction different from an extending direction of the main body section; and
a projection of the extension section of the corresponding initialization signal line on the base substrate overlaps with a projection of a corresponding connection line among the plurality of connection lines, and the extension section of the corresponding initialization signal line and the corresponding connection line are connected through a via hole in the overlapping area.

12. The array substrate according to claim 8 , further comprising:
a plurality of light-emitting control signal lines which are arranged in the first gate line layer, extend along the row direction and arranged at intervals along the column direction, and are used for providing light-emitting control signals to the sub-

Assignees

• Boe Technology Group Co Ltd

Inventors

• Han Long
• Liu Libin
• Huangfu Lujiang

Classifications

• G09G3/2074 Primary

  using sub-pixels · CPC title

• G09G3/3233

  with pixel circuitry controlling the current through the light-emitting element · CPC title

• G09G2300/0408

  Integration of the drivers onto the display substrate · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• G09G2300/0465

  Improved aperture ratio, e.g. by size reduction of the pixel circuit, e.g. for improving the pixel density or the maximum displayable luminance or brightness · CPC title