Request and floor interface for current control with correctness in an SOC

Patent metadata

Field	Value
Publication number	US-12197268-B2
Application number	US-202217573274-A
Country	US
Kind code	B2
Filing date	Jan 11, 2022
Priority date	Sep 24, 2021
Publication date	Jan 14, 2025
Grant date	Jan 14, 2025

Abstract

In an embodiment, a system may include a plurality of component circuits. The plurality of component circuits may include rate control circuits the control power consumption in the component circuits based on indications of power allocated to the component circuits. In an embodiment, the rate control circuits may transmit power requests for the component circuits and a floor request representing a minimum amount of power that may ensure reliable operation.

First claim

What is claimed is:

1. A system comprising:
a plurality of component circuits, wherein respective component circuits of the plurality of component circuits comprise respective rate control circuits; and
a power splitter circuit coupled to the plurality of component circuits, wherein:
the power splitter circuit is configured to allocate power to the plurality of component circuits based on a power budget for the system;
the respective rate control circuits are configured to generate respective power requests and respective floor requests for the power splitter circuit, wherein the respective floor requests indicate minimum amounts of power consumable by the corresponding component circuits;
the power splitter circuit is configured to ensure that the plurality of component circuits receive an allocation of power at least equal to a minimum of the respective floor requests and the respective power requests; and
the power splitter circuit is configured to allocate remaining power budget based on a power split policy and the respective power requests, wherein the power split policy includes:
a first level policy that specifies a split of the remaining power budget among respective types of component circuits; and
a second level policy that specifies, for an amount allocated to a given type of component circuit, a split of the amount among component circuits of the given type.

2. The system as recited in claim 1 wherein a given component circuit of the plurality of component circuits includes a power control circuit that is configured to cause reduced power consumption in the given component circuit, and wherein the respective floor request for the given component circuit is based on a maximum amount of reduced power consumption that the power control circuit is capable of causing.

3. The system as recited in claim 2 wherein the given component circuit experiences a leakage current in inactive transistors during use, and wherein the respective floor request for the given component circuit is further based on leakage power consumed through the leakage current.

4. The system as recited in claim 2 wherein the given component circuit further comprises a digital power estimation (DPE) circuit configured to estimate power consumption in the given component circuit, and wherein the respective power request is based on the estimated power consumption from the DPE circuit.

5. The system as recited in claim 4 wherein the DPE circuit is further configured to estimate leakage power, and to provide the respective floor request based on the leakage power and the maximum amount of reduced power consumption.

6. The system as recited in claim 1 wherein a physical interconnect between the power splitter circuit and the respective rate control circuit in a given component circuit of the plurality of component circuits includes a shared bus to transmit the respective power request and the respective floor request, and wherein the respective rate control circuit is configured to select one of the respective power request and the respective floor request to transmit on the shared bus.

7. The system as recited in claim 6 wherein the respective rate control circuit is configured to select the respective floor request based on a change in the respective floor request after a most recent transmission of the respective floor request.

8. The system as recited in claim 6 wherein the respective rate control circuit is configured to select the respective power request based on a change in the respective power request after a most recent transmission of the respective power request.

9. The system as recited in claim 6 wherein the respective rate control circuit is configured to select a least recently transmitted one of the respective floor request and the respective power request based on no change in the respective power request after the most recent transmission the respective power request and no change in the respective floor request after the most recent transmission of the respective floor request.

10. The system as recited in claim 6 wherein the power splitter circuit is configured to use a previously received request as a current request for a non-selected one of the respective power request and the respective floor request.

11. A system comprising:
a plurality of integrated circuits implemented on respective semiconductor substrates, wherein the plurality of integrated circuits are coupled via an inter-chip interconnect, wherein a respective integrated circuit of the plurality of integrated circuits comprises:
a plurality of component circuits, wherein respective component circuits of the plurality of component circuits comprise respective rate control circuits; and
a power splitter circuit coupled to the plurality of component circuits, wherein:
the power splitter circuit is configured to allocate power to the plurality of component circuits based on a power budget for the respective integrated circuit;
the respective rate control circuits are configured to generate respective power requests and respective floor requests, wherein the respective floor requests indicate minimum amounts of power consumable by the corresponding component circuits;
the power splitter circuit is configured to ensure that the plurality of component circuits receive an allocation of power at least equal to a minimum of the respective floor requests and the respective power requests;
the power splitter circuit is configured to allocate remaining power budget based on a power split policy and the respective power requests, wherein the power split policy includes:
a first level policy that specifies a split of the remaining power budget among respective types of component circuits; and
a second level policy that specifies, for an amount allocated to a given type of component circuit, a split of the amount among component circuits of the given type; and

the power splitter circuit is configured to transmit an indication of an unallocated portion of the remaining power budget to the power splitter circuit in another integrated circuit of the plurality of integrated circuits over the inter-chip interconnect.

12. The system as recited in claim 11 wherein the power splitter circuit in the respective integrated circuit is configured to receive a second indication of an unallocated portion of the remaining power budget from the power splitter circuit in another integrated circuit of the plurality of integrated circuits, and wherein the power splitter circuit is configured to include the unallocated portion in a subsequent power allocation.

13. The system as recited in claim 11 further comprising a plurality of voltage regulators, wherein a given voltage regulator of the plurality of voltage regulators is configured to supply power to a subset of the plurality of integrated circuits, and wherein the power splitter circuits in the respective integrated circuits in the subset are configured to transmit the indications of the unallocated portion among the subset.

14. A method comprising:
generating respective power requests and respective floor requests for a power splitter circuit in a system by respective rate control circuits in respective component circuits of a plurality of component circuits in the system, wherein the respective floor requests indicate minimum amounts of power consumable by the corresponding component circuits; and
allocating power to the plurality of component circuits by the power splitter circuit, wherein the allocating comprises:
ensuring that the plurality of component circuits receive an allocation of power at least equal to a minimum of the respect

Assignees

• Apple Inc

Inventors

• Rajwan Doron
• Sodhi Inder M
• Cox Keith
• Cho Jung Wook
• Park Kevin I
• Kuzi Tal

Classifications

• G06F1/3206

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title

• G06F1/324

  by lowering clock frequency · CPC title

• G06F1/3296

  by lowering the supply or operating voltage · CPC title

• G06F1/26

  Power supply means, e.g. regulation thereof (for memories G11C) · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title