Power management for a memory device

Patent metadata

Field	Value
Publication number	US-12197264-B2
Application number	US-202017094579-A
Country	US
Kind code	B2
Filing date	Nov 10, 2020
Priority date	Nov 10, 2020
Publication date	Jan 14, 2025
Grant date	Jan 14, 2025

Abstract

Methods, systems, and devices for power management for a memory device are described. For example, a memory device may include one or more memory dies and may be configured to operate using a first supply voltage and a second supply voltage. The first supply voltage may be associated with a first defined voltage range, and the second supply voltage may be associated with a second defined voltage range. The memory device may include a power management integrated circuit (PMIC) that is coupled with the one or more memory dies and provides the supply voltages to the one or more memory dies. The PMIC may be configured to provide, to the one or more memory dies, a first voltage that is within the first defined voltage range as the first supply voltage and a second voltage that is outside the second defined voltage range as the second supply voltage.

First claim

What is claimed is:

1. A system, comprising:
a memory die configured to exchange signaling with a host device in accordance with a memory standard and to operate using a first supply voltage and a second supply voltage, wherein the first supply voltage is associated with a first defined voltage range specified by the memory standard and the second supply voltage is associated with a second defined voltage range specified by the memory standard; and
a power management integrated circuit (PMIC) coupled with the memory die and configured to:
read a first value stored in a register and a second value stored in the register, wherein the first value indicates a first voltage for the first supply voltage and the second value indicates a second voltage for the second supply voltage;
provide, to the memory die as the first supply voltage and after reading the first value and the second value, the first voltage that is within the first defined voltage range specified by the memory standard based at least in part on reading the first value stored in the register; and
provide, to the memory die as the second supply voltage, the second voltage that is outside the second defined voltage range specified by the memory standard concurrent with providing the first voltage based at least in part on reading the second value stored in the register.

2. The system of claim 1 , wherein the PMIC is further configured to:
identify the second voltage that is outside the second defined voltage range during an initialization of the system, wherein providing the second voltage is based at least in part on the identifying.

3. The system of claim 2 , further comprising:
the register coupled with or included in the PMIC and configured to store the first value indicating the first voltage that is within the first defined voltage range and the second value indicating the second voltage that is outside the second defined voltage range, wherein the identifying is based at least in part on the register storing the first value indicating the first voltage and the second value indicating the second voltage.

4. The system of claim 3 , wherein:
the memory die is configured to be coupled with the host device; and
the first value and the second value are unalterable by the host device.

5. The system of claim 1 , wherein the PMIC is configured to provide the second voltage based at least in part on the memory die satisfying a performance threshold when using the second voltage as the second supply voltage.

6. The system of claim 1 , wherein:
a dual in-line memory module (DIMM) comprises the PMIC, the memory die,
and one or more additional memory dies each configured to operate using the first supply voltage and the second supply voltage;
the memory die and the one or more additional memory dies each comprise dynamic random access memory (DRAM) memory cells; and
the PMIC is further configured to:
provide, to each of the one or more additional memory dies as the first supply voltage, the first voltage that is within the first defined voltage range; and
provide, to each of the one or more additional memory dies as the second supply voltage, the second voltage that is outside the second defined voltage range.

7. The system of claim 1 , wherein the second voltage is below the second defined voltage range.

8. The system of claim 1 , wherein the second voltage is above the second defined voltage range.

9. A method, comprising:
reading, by a power management integrated circuit (PMIC) that is coupled with a memory die configured to exchange signaling with a host device in accordance with a memory standard, a first value stored in a register and a second value stored in the register, wherein the first value indicates a first voltage for a first supply voltage and the second value indicates a second voltage for a second supply voltage;
generating, using the PMIC and after reading the first value and the second value, the first voltage that is within a first defined voltage range specified by the memory standard corresponding to the first supply voltage for the memory die based at least in part on reading the first value stored in the register;
generating, using the PMIC, the second voltage that is outside a second defined voltage range specified by the memory standard corresponding to the second supply voltage for the memory die based at least in part on reading the second value stored in the register; and
operating the memory die using, concurrently, the first voltage as the first supply voltage and the second voltage as the second supply voltage.

10. The method of claim 9 , further comprising:
operating one or more additional memory dies coupled with the PMIC using the first voltage and the second voltage as one or more respective first supply voltages and one or more second supply voltages for the one or more additional memory dies.

11. The method of claim 9 , wherein generating the second voltage further comprises:
identifying the second voltage during an initialization procedure executed prior to operating the memory die.

12. The method of claim 11 , further comprising:
storing the first value indicating the first voltage that is within the first defined voltage range and the second value indicating the second voltage that is outside the second defined voltage range to the register coupled with or included in the PMIC, wherein the identifying is based at least in part on storing the first value indicating the first voltage and the second value indicating the second voltage to the register.

13. The method of claim 12 , wherein:
the memory die is configured to be coupled with the host device; and
the first value and the second value are unalterable by the host device.

14. The method of claim 9 , wherein the second voltage is below the second defined voltage range.

15. The method of claim 9 , wherein the second voltage is above the second defined voltage range.

16. The method of claim 9 , wherein generating the second voltage using the PMIC is based at least in part on the memory die satisfying a performance threshold when using the second voltage as the second supply voltage.

17. A memory device, comprising:
a memory die configured to exchange signaling with a host device in accordance with a memory standard; and
one or more controllers coupled with the memory die, wherein the one or more controllers are configured to cause the memory device to:
read, by a power management integrated circuit (PMIC) that is coupled with the memory die, a first value stored in a register and a second value stored in the register, wherein the first value indicates a first voltage for a first supply voltage and the second value indicates a second voltage for a second supply voltage;
generate, using the PMIC and after reading the first value and the second value, the first voltage that is within a first defined voltage range specified by the memory standard corresponding to the first supply voltage for the memory die based at least in part on reading the first value stored in the register;
generate, using the PMIC, the second voltage that is outside a second defined voltage range specified by the memory standard corresponding to the second supply voltage for the memory die based at least in part on reading the second value stored in the register; and
operate the memory die using, concurrently, the first voltage as the first supply voltage and the second voltage as the second supply voltage.

18. The memory device of claim 17 , wherein the one or more controllers are further configured to

Assignees

• Micron Technology Inc

Inventors

• Rehmeyer James S
• Howe Gary L
• Wiscombe Miles S
• Stave Eric J

Classifications

• G11C11/4074

  Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits · CPC title

• G06F1/3296

  by lowering the supply or operating voltage · CPC title

• G06F1/3275

  Power saving in memory, e.g. RAM, cache · CPC title

• G11C29/56

  External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor · CPC title

• G11C29/50

  Marginal testing, e.g. race, voltage or current testing · CPC title