Display panel

Patent metadata

Field	Value
Publication number	US-12193312-B2
Application number	US-202318382051-A
Country	US
Kind code	B2
Filing date	Oct 19, 2023
Priority date	Nov 30, 2018
Publication date	Jan 7, 2025
Grant date	Jan 7, 2025

Abstract

A display panel includes a substrate including a first region, a second region, a non-display area that surrounds the first region and the second region, and a display area that surrounds the non-display area; a plurality of pixels arranged on the display area; a plurality of dummy pixels arranged on the non-display area and emitting no light; and a plurality of signal lines configured to electrically connect the plurality of pixels to the plurality of dummy pixels. Some of the plurality of dummy pixels are arranged between the first region and the second region.

First claim

What is claimed is:

1. A display panel comprising:
a substrate including a first region, a second region, a non-display area that surrounds the first region and the second region, and a display area that surrounds the non-display area;
a plurality of display elements on the display area;
a plurality of pixel circuits connected to the each of the plurality of display elements on the display area;
a plurality of dummy pixel circuits disposed on the non-display area;
a pixel defining layer disposed over the plurality of pixel circuits and the plurality of dummy pixel circuits,
wherein the pixel defining layer comprises a plurality of openings corresponding to each of the plurality of display elements, and
wherein the pixel defining layer entirely covers the non-display area and has a flat upper surface on an area corresponding to the plurality of dummy pixel circuits.

2. The display panel of claim 1 , further comprising an organic emission layer arranged within the plurality of openings of the pixel defining layer on the display area,
wherein the organic emission layer is arranged on the flat upper surface of the pixel defining layer on the non-display area.

3. The display panel of claim 1 , further comprising
a first common layer, an organic emission layer, and a second common layer sequentially stacked on each other and arranged within the plurality of openings of the pixel defining layer on the display area,
wherein the first common layer and the second common layer contact each other on the flat upper surface of the pixel defining layer on the non-display area.

4. The display panel of claim 1 ,
wherein each of the plurality of display elements comprises a pixel electrode, an intermediate layer arranged within the opening of the pixel defining layer, and an opposite electrode arranged on the intermediate layer,
wherein the opening extends to the pixel electrode, and
the opposite electrode contacts the flat upper surface of the pixel defining layer on the non-display area.

5. The display panel of claim 1 , further comprising a conductive layer overlapping with the dummy pixel circuit, wherein the conductive layer is disposed on a same layer as a pixel electrode of the display elements.

6. The display panel of claim 1 , further comprising a plurality of signal lines connecting to some of the plurality of pixel circuits and some of the plurality of dummy pixel circuits.

7. The display panel of claim 6 , wherein the plurality of dummy pixel circuits includes a first dummy pixel circuit and a second dummy pixel circuit,
the plurality of signal lines includes a first signal line and a second signal line spaced apart from the first signal line in a second direction crossing a first direction,
the first signal line connects to the first dummy pixel circuit and extends in the first direction,
the second signal line connects to the second dummy pixel circuit and extends in the first direction, and
the first signal line and the second signal line are connected by a connection wire.

8. The display panel of claim 7 , further comprising a detouring line connecting to the connection wire, the detouring line detouring around the first region.

9. The display panel of claim 1 , wherein some of the plurality of dummy pixel circuits are arranged between the first region and the second region.

10. The display panel of claim 1 , wherein the plurality of dummy pixel circuits are arranged to surround the first region and the second region.

11. A display panel comprising:
a substrate including a first region, a second region, a non-display area that surrounds the first region and the second region, and a display area that surrounds the non-display area;
a plurality of display elements on the display area;
a plurality of pixel circuits connected to the each of the plurality of display elements on the display area;
a plurality of dummy pixel circuits disposed on the non-display area;
a plurality of signal lines connecting to some of the plurality of pixel circuits and some of the plurality of dummy pixel circuits;
a pixel defining layer disposed over the plurality of pixel circuits and the plurality of dummy pixel circuits,
wherein the pixel defining layer comprises a plurality of openings corresponding to each of the plurality of display elements, and
wherein the pixel defining layer entirely covers the non-display area and has a flat upper surface on an area corresponding to the non-display area.

12. The display panel of claim 11 , further comprising an organic emission layer arranged within the plurality of openings of the pixel defining layer on the display area,
wherein the organic emission layer is arranged on the flat upper surface of the pixel defining layer on the non-display area.

13. The display panel of claim 11 , further comprising a first common layer, an organic emission layer, and a second common layer sequentially stacked on each other and arranged within the plurality of openings of the pixel defining layer on the display area,
wherein the first common layer and the second common layer contact each other on the flat upper surface of the pixel defining layer on the non-display area.

14. The display panel of claim 11 ,
wherein each of the plurality of display elements comprises a pixel electrode, an intermediate layer arranged within the opening of the pixel defining layer, and an opposite electrode arranged on the intermediate layer,
wherein the opening extends to the pixel electrode, and
the opposite electrode contacts the flat upper surface of the pixel defining layer on the non-display area.

15. The display panel of claim 11 , further comprising a conductive layer overlapping with the dummy pixel circuit, wherein the conductive layer is disposed on a same layer as a pixel electrode of the display elements.

16. The display panel of claim 11 , wherein each of the plurality of dummy circuits comprises at least one dummy transistor.

17. The display panel of claim 11 , wherein the plurality of dummy pixel circuits includes a first dummy pixel circuit and a second dummy pixel circuits,
the plurality of signal lines includes a first signal line and a second signal line spaced apart from the first signal line in a second direction crossing a first direction,
the first signal line connects to the first dummy pixel circuit and extends in the first direction,
the second signal line connects to the second dummy pixel circuit and extends in the first direction, and
the first signal line and the second signal line are connected by a connection wire.

18. The display panel of claim 17 , further comprising a detouring line connecting to the connection wire, the detouring line detouring around the first region.

19. The display panel of claim 11 , wherein some of the plurality of dummy pixel circuits are arranged between the first region and the second region.

20. The display panel of claim 11 , wherein the plurality of dummy pixel circuits are arranged to surround the first region and the second region.

Assignees

• Samsung Display Co Ltd

Inventors

• An Junyong
• Park Hyunae
• Park Hyungjun
• Sung Seungwoo
• Yoon Youngsoo
• Youn Ilgoo
• Lee Jieun
• In Yunkyeong
• Jang Donghyeon
• Jo Junyoung

Classifications

• H10K59/88 Primary

  Dummy elements, i.e. elements having non-functional features · CPC title

• H10K59/131 Primary

  Interconnections, e.g. wiring lines or terminals · CPC title

• G09G2300/0413

  Details of dummy pixels or dummy lines in flat panels · CPC title

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title

• H10K59/121

  characterised by the geometry or disposition of pixel elements · CPC title