Semiconductor structure and method for forming semiconductor structure

Patent metadata

Field	Value
Publication number	US-12193222-B2
Application number	US-202217580771-A
Country	US
Kind code	B2
Filing date	Jan 21, 2022
Priority date	Jul 27, 2021
Publication date	Jan 7, 2025
Grant date	Jan 7, 2025

Abstract

The embodiment of the application provides a semiconductor structure and a method for forming a semiconductor structure. The method includes: a substrate structure is provided, in which the substrate structure at least including bit line structures and a plurality of landing pads, each of the plurality of landing pads is formed around a respective one of the bit line structures and covers a part of the respective one of the bit line structures, and a gap is formed between each two adjacent landing pads of the plurality of landing pads; and capacitive structures are formed on top surfaces of the plurality of landing pads and in the gaps.

First claim

The invention claimed is:

1. A method for forming a semiconductor structure, comprising:
providing a substrate structure, wherein the substrate structure at least comprises bit line structures and a plurality of landing pads, each of the plurality of landing pads is formed around a respective one of the bit line structures and covers a part of the respective one of the bit line structures, and a gap is formed between each two adjacent landing pads of the plurality of landing pads; and
forming capacitive structures on top surfaces of the plurality of landing pads and in the gaps.

2. The method of claim 1 , forming the capacitive structures on the top surfaces of the plurality of landing pads and in the gaps comprising:
forming first insulating layers in the gaps, the first insulating layers being flush with surfaces of the plurality of landing pads;
forming a stack structure on the surfaces of the plurality of landing pads and surfaces of the first insulating layers; and
processing the stack structure and the first insulating layers to form the capacitive structures.

3. The method of claim 2 , wherein the stack structure comprises a sacrificial layer and a supporting layer, wherein processing the stack structure and the first insulating layers to form the capacitive structures comprises:
patterning the stack structure to form capacitive holes in the stack structure on the surfaces of the plurality of landing pads;
forming first electrode layers on inner walls of the capacitive holes and on a surface of the patterned stack structure;
patterning the supporting layer to form openings between adjacent capacitive holes;
etching the sacrificial layer and the first insulating layers through the openings; and
forming the capacitive structures in the patterned supporting layer.

4. The method of claim 3 , forming the capacitive structures in the patterned supporting layer comprising:
sequentially depositing dielectric layers and second electrode layers on surfaces of the first electrode layers; and
depositing a conductive material filling a clearance between the second electrode layers and covering an upper surface of the stack structure, wherein the first electrode layers, the dielectric layers, the second electrode layers and the conductive material form the capacitive structures.

5. The method of claim 4 , wherein the sacrificial layer comprises a first sacrificial layer and a second sacrificial layer, and the supporting layer comprises a first supporting layer and a second supporting layer,
wherein the method further comprises: forming a first mask layer on a surface of the second supporting layer,
wherein patterning the stack structure to form capacitive holes in the stack structure on the surfaces of the plurality of landing pads comprises:
patterning the first mask layer; and
etching the second supporting layer, the second sacrificial layer, the first supporting layer and the first sacrificial layer on the surfaces of the plurality of landing pads by using the patterned first mask layer as a mask to form the capacitive holes.

6. The method of claim 5 , wherein the patterned stack structure comprises the first sacrificial layer, the first supporting layer, the second sacrificial layer and the second supporting layer stacked onto one another, and the first mask layer and the first electrode layers are formed on the surface of the patterned stack structure,
wherein patterning the supporting layer to form openings between adjacent capacitive holes and etching the sacrificial layer and the first insulating layers through the openings comprise:
forming a first opening in the first mask layer and the second supporting layer;
removing the second sacrificial layer through the first opening;
forming a second opening in the first supporting layer; and
removing the first sacrificial layer and the first insulating layer through the second opening.

7. The method of claim 6 , wherein the first opening and the second opening are formed through a dry etching process.

8. The method of claim 6 , wherein a side wall of each bit line structure is formed with a first spacer layer, a second spacer layer and a sacrificial spacer layer located between the first spacer layer and the second spacer layer, and the first insulating layer is connected with the sacrificial spacer layer, wherein the method further comprises:
removing the sacrificial spacer layer when the first sacrificial layer and the first insulating layer are removed through the second opening,
wherein the first sacrificial layer and the sacrificial spacer layer are formed of a same material.

9. The method of claim 8 , wherein the second sacrificial layer, the first sacrificial layer, the first insulating layer and the first spacer layer are removed through a wet etching process.

10. The method of claim 8 , wherein the substrate structure further comprises storage node contacts, and each of the storage node contacts is formed around a respective one of the bit line structures and is in contact with a respective one of the plurality of landing pads, wherein the plurality of landing pads and the gaps are formed by:
forming a conductive layer covering the bit line structures on a surface of each storage node contact, wherein a top surface of the conductive layer exceeds a top surface of each bit line structure;
forming a patterned second mask layer on a surface of the conductive layer; and
etching a part of the conductive layer and a part of the first spacer layer through the patterned second mask layer until the sacrificial spacer layer is exposed, to form the plurality of landing pads located on surfaces of the storage node contacts and the gaps between adjacent landing pads, wherein a section of each gap along a first direction is stepped, and the first direction is perpendicular to an extension direction of the bit line structures and an arrangement direction of the bit line structures.

11. The method of claim 8 , wherein each of the bit line structures comprises a bit line contact layer, a bit line metal layer and a bit line mask layer which are sequentially stacked onto one another from bottom to top along a first direction, and the first direction is perpendicular to an extension direction of the bit line structures and an arrangement direction of the bit line structures, wherein the method further comprises:
forming a second insulating layer between each two adjacent landing pads of the plurality of landing pads, wherein the second insulating layer is flush with the surfaces of the plurality of landing pads; and
etching the second insulating layer and a part of the bit line mask layer to form the gaps, wherein a section of each gap along the first direction is U-shaped.

12. A semiconductor structure, comprising:
a substrate structure, wherein the substrate structure at least comprises bit line structures and a plurality of landing pads, each of the plurality of landing pads is formed around a respective one of the bit line structures and covers a part of the respective one of the bit line structures, and a gap is formed between each two adjacent landing pads of the plurality of landing pads; and
capacitive structures located on top surfaces of the plurality of landing pads and in the gaps.

13. The semiconductor structure of claim 12 , wherein a section of each gap along a first direction is stepped, the first direction is perpendicular to an extension direction of the bit line structures and an arrangement direction of the bit line structures, each of the bit line structures comprises a bit line contact layer, a bit line metal layer and a bit line mask layer which are sequentially

Assignees

• Changxin Memory Tech Inc

Inventors

• Li Ran
• Duan Leilei
• Jin Xing
• Cheng Ming

Classifications

• H10B12/312

  with a bit line higher than the capacitor · CPC title

• H10B12/033

  the capacitor extending over the transistor · CPC title

• H10B12/315

  with the capacitor higher than a bit line · CPC title

• H10B12/50 Primary

  Peripheral circuit region structures · CPC title

• H10D1/716 Primary

  having vertical extensions · CPC title