Semiconductor devices

Patent metadata

Field	Value
Publication number	US-2022139921-A1
Application number	US-202117372634-A
Country	US
Kind code	A1
Filing date	Jul 12, 2021
Priority date	Nov 3, 2020
Publication date	May 5, 2022
Grant date	—

Abstract

A semiconductor device includes a substrate including an active region, a first bitline structure and a second bitline structure that extend side by side on the substrate, a storage node contact electrically connected to the active region between the first and second bitline structures, a lower landing pad between the first and second bitline structures and on the storage node contact, an upper landing pad in contact with the first bitline structure and electrically connected to the lower landing pad, and a capping insulating layer. A lower surface of the upper landing pad in contact with the first bitline structure and a lower surface of the capping insulating layer in contact with the lower landing pad each include a portion in which a horizontal separation distance is increased from the adjacent upper landing pad in a direction toward the substrate.

First claim

1 . A semiconductor device comprising:
a substrate including a first active region and a second active region; a bitline structure that extends in one direction on the substrate and electrically connected to the first active region; a storage node contact on a sidewall of the bitline structure and electrically connected to the second active region; a spacer structure between the bitline structure and the storage node contact; a lower landing pad on the storage node contact and in contact with a sidewall of the spacer structure; an upper landing pad on the bitline structure, the spacer structure, and the lower landing pad to be electrically connected to the lower landing pad; a capping insulating layer on the lower landing pad and in contact with a sidewall of the upper landing pad; and a capacitor structure on the capping insulating layer and electrically connected to the upper landing pad, wherein the upper landing pad includes a first region that overlaps the bitline structure in a vertical direction and a second region that overlaps the lower landing pad in the vertical direction, and wherein a lower end of the second region is closer to the substrate than a lower end of the first region.

2 . The semiconductor device of claim 1 , wherein the upper landing pad has a first sidewall and a second sidewall opposing each other,
wherein the first and second regions include the first and second sidewalls, respectively, and wherein a lower surface of the upper landing pad that connects the first and second sidewalls to each other in a lower portion of the upper landing pad includes a first portion in which a vertical depth of the upper landing pad is increased in a direction toward the lower landing pad.

3 . The semiconductor device of claim 2 , wherein the first portion of the lower surface of the upper landing pad includes at least one sloped portion and/or curved portion, wherein the first portion is in contact with the bitline structure, and wherein the first portion is connected to the first sidewall.

4 . The semiconductor device of claim 2 , wherein the lower surface of the upper landing pad further includes a second portion in contact with the lower landing pad.

5 . The semiconductor device of claim 4 , wherein the second portion of the lower surface of the upper landing pad includes at least one sloped portion and/or curved portion, and wherein the second portion is connected to the second sidewall.

6 . The semiconductor device of claim 1 , wherein each of the lower landing pad and the upper landing pad include at least one of polycrystalline silicon (Si), titanium (Ti), tantalum (Ta), tungsten (W), ruthenium (Ru), copper (Cu), molybdenum (Mo), platinum (Pt), nickel (Ni), cobalt (Co), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), and tungsten nitride (WN).

7 . The semiconductor device of claim 1 , wherein the upper landing pad has a first sidewall and a second sidewall opposing each other, and wherein a lower surface of the capping insulating layer is connected to a sidewall of the capping insulating layer in contact with the second sidewall of the upper landing pad, and includes a first portion in which a horizontal separation distance is increased from the upper landing pad in a downward direction.

8 . The semiconductor device of claim 7 , wherein the first portion of the lower surface of the capping insulating layer is in contact with the lower landing pad.

9 - 10 . (canceled)

11 . A semiconductor device comprising:
a substrate including an active region; a first bitline structure and a second bitline structure that extend side by side on the substrate; a storage node contact electrically connected to the active region between the first and second bitline structures; a lower landing pad between the first and second bitline structures and on the storage node contact; an upper landing pad in contact with the first bitline structure and electrically connected to the lower landing pad; and a capping insulating layer in contact with the second bitline structure, the upper landing pad, and the lower landing pad, wherein a lower surface of the upper landing pad in contact with the first bitline structure includes a portion in which a horizontal separation distance is increased from the adjacent capping insulating layer in a direction toward the substrate, and wherein a lower surface of the capping insulating layer in contact with the lower landing pad includes a portion in which a horizontal separation distance is increased from the adjacent upper landing pad in the direction toward the substrate.

12 . The semiconductor device of claim 11 , wherein a lowermost portion of the upper landing pad is in contact with the lower landing pad.

13 . The semiconductor device of claim 11 , wherein the portion of the lower surface of the upper landing pad includes at least one of a portion having a slope and a curved portion.

14 . The semiconductor device of claim 13 , wherein the portion of the lower surface of the upper landing pad is in contact with the first bitline structure.

15 . The semiconductor device of claim 11 , wherein the portion of the lower surface of the capping insulating layer includes at least one sloped portion and/or curved portion.

16 . The semiconductor device of claim 15 , wherein the portion of the lower surface of the capping insulating layer is in contact with the lower landing pad.

17 . The semiconductor device of claim 11 , wherein a lower portion of the upper landing pad has a pointed shape in the direction toward the substrate.

18 . The semiconductor device of claim 11 , wherein a lower portion of the capping insulating layer has a pointed shape in the direction toward the substrate.

19 . (canceled)

20 . A semiconductor device comprising:
a substrate including at least two first active regions and at least two second active regions; at least two bitlines that are spaced apart from each other and that extend side by side on the substrate, and respectively electrically connected to the at least two first active regions; at least two bitline capping patterns respectively on the at least two bitlines; spacer structures on sidewalls of the bitlines and sidewalls of the bitline capping patterns; at least two storage node contacts between the spacer structures, and respectively electrically connected to the at least two second active regions; lower landing pads respectively on the at least two storage node contacts; upper landing pads respectively electrically connected to the lower landing pads; and a capping insulating layer between the upper landing pads and having a lower end in contact with upper surfaces of the spacer structures, wherein at least some of the upper landing pads include a first region in contact with one of the at least two bitline capping patterns and having a lower end at a first vertical depth from an upper surface, and a second region in contact with the lower landing pad and having a lower end at a second vertical depth, greater than the first vertical depth, from the upper surface.

21 . The semiconductor device of claim 20 , wherein a portion of a lower surfaces of the upper landing pads in contact with one of the bitline capping patterns includes at least one sloped portion and/or curved portion, and
wherein a portion of a lower surface of the capping insulating layer in contact with the lower landing pads includes at least one sloped portion and/or curved portion.

22 . The semiconduct

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Euna
• Kim Keunnam
• Lee Kiseok
• Choi Wooyoung
• Han Sunghee

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H01L27/10885

  Electricity · mapped topic

• H01L27/10888

  Electricity · mapped topic

• H01L27/10855

  Electricity · mapped topic

• H01L27/10814 Primary

  Electricity · mapped topic