Reducing off-state leakage in semiconductor devices

Patent metadata

Field	Value
Publication number	US-12191349-B2
Application number	US-201716649287-A
Country	US
Kind code	B2
Filing date	Dec 15, 2017
Priority date	Dec 15, 2017
Publication date	Jan 7, 2025
Grant date	Jan 7, 2025

Abstract

Material systems for source region, drain region, and a semiconductor body of transistor devices in which the semiconductor body is electrically insulated from an underlying substrate are selected to reduce or eliminate a band to band tunneling (“BTBT”) effect between different energetic bands of the semiconductor body and one or both of the source region and the drain region. This can be accomplished by selecting a material for the semiconductor body with a band gap that is larger than a band gap for material(s) selected for the source region and/or drain region.

First claim

What is claimed is:

1. An integrated circuit device comprising:
a body above a substrate, the body having a top surface and a bottom surface opposite the top surface, the body comprising a first semiconductor material having a first band gap between a conduction band and a valence band of the first semiconductor material;
an insulation structure between the substrate and the bottom surface of the body;
a gate structure including a gate dielectric structure having a portion on the body and a portion on the insulation structure, wherein the portion of the gate dielectric structure on the insulation structure is continuous along the insulation structure beneath the bottom surface of the body, the gate structure further including a gate electrode structure on the gate dielectric structure, wherein the gate structure is completely wrapped around a channel region of the body; and
a source region and a drain region, the body between the source region and the drain region, wherein at least one of the source region and the drain region comprises a second semiconductor material having a second band gap between a conduction band and a valence band of the second semiconductor material, the second band gap less than the first band gap of the body, and wherein the insulation structure extends vertically beneath the source region and the drain region.

2. The integrated circuit device of claim 1 , wherein:
the first band gap is greater than 1.3 eV; and
the second band gap less than 0.75 eV.

3. The integrated circuit device of claim 1 , wherein:
the first band gap is from 1.3 eV to 2.2 eV; and
the second band gap is from 0.15 eV to 0.75 eV.

4. The integrated circuit device of claim 1 , wherein:
the first band gap is from 0.67 eV to 1.3 eV; and
the second band gap is less than 0.73 eV.

5. The integrated circuit device of claim 1 , wherein:
the first band gap is from 0.2 eV to 0.3 eV; and
the second band gap is less than 0.2 eV.

6. The integrated circuit device of claim 1 , wherein the body has a width of 10 nm or less.

7. The integrated circuit device of claim 1 , wherein:
the source region, the drain region, and the body comprise majority charge carriers having energies in one of the conduction band or the valence band; and
the one of the conduction band or the valence band in which the majority charge carrier have energies is overlapping between the body and at least one of the source region and the drain region.

8. The integrated circuit device of claim 7 , wherein:
the majority charge carriers are electrons; the conduction bands of the source region, the drain region, and the body have at least some overlap in energies; and
the valence band of the body does not have any overlap in energy with at least one of the source region and the drain region.

9. The integrated circuit device of claim 7 , wherein:
the majority charge carriers are holes; the valence bands of the source region, the drain region, and the body have at least some overlap in energies; and
the conduction band of the body does not have any overlap in energy with at least one of the source region and the drain region.

10. The integrated circuit device of claim 1 , wherein:
the body comprises indium and phosphorous; and
at least one of the source region and the drain region comprises indium, and arsenic.

11. The integrated circuit device of claim 10 , wherein:
the body further comprises gallium; and
at least one of the source region and the drain region further comprises at least one of gallium and antimony.

12. The integrated circuit device of claim 1 , wherein:
the body comprises indium, gallium, arsenic, and antimony; and
at least one of the source region and the drain region comprises indium and at least one of arsenic and antimony.

13. The integrated circuit device of claim 1 , wherein:
the body comprises indium, gallium, phosphorous, and antimony; and
at least one of the source region and the drain region comprises indium and at least one of arsenic and antimony.

14. The integrated circuit device of claim 13 , wherein at least one of the source region and the drain region further comprises gallium.

15. The integrated circuit device of claim 1 , wherein the body comprises antimony and at least one of aluminum and gallium.

16. The integrated circuit device of claim 15 , wherein at least one of the source region and the drain region comprises antimony and one of indium and gallium.

17. The integrated circuit device of claim 15 , wherein at least one of the source region and the drain region comprises germanium.

18. The integrated circuit device of claim 1 , wherein:
the body comprises one or both of silicon and germanium; and
at least one of the source region and the drain region comprises germanium.

19. The integrated circuit device of claim 1 , wherein a majority of the first band gap is above a Fermi level associated with an energy band of a majority charge carrier.

20. The integrated circuit device of claim 1 , wherein:
a majority charge carrier is an electron;
the valence bands of the source region, the drain region, and the body have an energy offset therebetween; and
the conduction bands of the source region, the drain region, and the body do not have an energy offset therebetween.

21. The integrated circuit device of claim 1 , wherein:
a majority charge carrier is a hole;
the valence bands of the source region, the drain region, and the body do not have an energy offset therebetween; and
the conduction bands of the source region, the drain region, and the body have an energy offset therebetween.

22. An integrated circuit device comprising:
a nanowire comprising a first semiconductor material having a first band gap between a conduction band and a valence band of the first semiconductor material;
an insulation structure below the nanowire;
a gate structure completely wrapped around the nanowire, that gate structure including a gate dielectric structure having a portion on the nanowire and a portion on the insulation structure, wherein the portion of the gate dielectric structure on the insulation structure is continuous along the insulation structure beneath the nanowire, the gate structure further including a gate electrode structure on the gate dielectric structure; and
a source region and a drain region, the nanowire between the source region and the drain region, wherein at least one of the source region and the drain region comprises a second semiconductor material having a second band gap between a conduction band and a valence band of the second semiconductor material, the second band gap less than the first band gap of the nanowire, and wherein the insulation structure extends vertically beneath the source region and the drain region.

23. The integrated circuit device of claim 22 , wherein the first semiconductor material comprises a group III-V semiconductor material, and the second semiconductor material comprises one or both of a group IV semiconductor material and a group III-V semiconductor material.

24. An integrated circuit device comprising:
a body having a top surface and a bottom surface opposite the top surface, the body comprising a first semiconductor material having a first band gap between a conduction band and a valence band of the first semiconductor material;
an insulation structure below the body;
a gate structure including a gate dielectric structure having a portion on the body and

Assignees

• Intel Corp

Inventors

• Basu Dipanjan
• Weber Cory E
• Weber Justin R
• Ma Sean T
• Kennel Harold W
• Sung Seung Hoon
• Glass Glenn A
• Kavalieros Jack T
• Ghani Tahir

Classifications

• H10D84/853

  comprising FinFETs · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D84/017

  Manufacturing their source or drain regions, e.g. silicided source or drain regions · CPC title

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H10D84/834

  comprising FinFETs · CPC title