Method for manufacturing semiconductor device
US-9318512-B2 · Apr 19, 2016 · US
Semiconductor device, display module, and electronic device
US12190842B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-12190842-B2 |
| Application number | US-202218083282-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 16, 2022 |
| Priority date | Apr 24, 2014 |
| Publication date | Jan 7, 2025 |
| Grant date | Jan 7, 2025 |
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- Title
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Abstract
Official abstract text for this publication.
A first flipflop outputs a first signal synchronized with a first clock signal. In the first transistor, the first clock signal is input to a first terminal and the second signal is output from a second terminal. In the fourth transistor, a first signal is input to a first terminal and a second terminal is electrically connected to a gate of the first transistor. In the sixth transistor, the third signal is input to a first terminal, a second terminal is electrically connected to the gate of the fourth transistor, and the gate of the sixth transistor is electrically connected to the first terminal.
First claim
Opening claim text (preview).
What is claimed is: 1. A semiconductor device comprising: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor and a ninth transistor, wherein one of a source and a drain of the first transistor is electrically connected to a clock signal line, wherein the other of the source and the drain of the first transistor is electrically connected to an output terminal, wherein one of a source and a drain of the second transistor is electrically connected to the output terminal, wherein the other of the source and the drain of the second transistor is electrically connected to a first power supply line, wherein one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor, wherein the other of the source and the drain of the third transistor is electrically connected to a second power supply line, wherein one of a source and a drain of the fourth transistor is electrically connected to the gate of the first transistor, wherein one of a source and a drain of the fifth transistor is electrically connected to the gate of the first transistor, wherein one of a source and a drain of the sixth transistor is electrically connected to a gate of the fourth transistor, wherein the other of the source and the drain of the sixth transistor is electrically connected to a first signal line, wherein a gate of the sixth transistor is electrically connected to the other of the source and the drain of the sixth transistor, wherein one of a source and a drain of the seventh transistor is electrically connected to the gate of the fourth transistor, wherein one of a source and a drain of the eighth transistor is electrically connected to a gate of the fifth transistor, wherein the other of the source and the drain of the eighth transistor is electrically connected to a second signal line, wherein a gate of the eighth transistor is electrically connected to the other of the source and the drain of the eighth transistor, wherein one of a source and a drain of the ninth transistor is electrically connected to the gate of the fifth transistor, wherein a gate of the ninth transistor is electrically connected to a gate of the seventh transistor, wherein the fourth transistor is configured to control a potential of the gate of the first transistor, wherein the fifth transistor is configured to control a potential of the gate of the first transistor, wherein the seventh transistor is configured to control a potential of the gate of the fourth transistor, and wherein the ninth transistor is configured to control a potential of the gate of the fifth transistor.
Assignees
Inventors
Classifications
using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title
Organisation of a multiplicity of shift registers · CPC title
using devices arranged in a shift register · CPC title
using bistable devices (H03K5/15093 takes precedence) · CPC title
using digital techniques · CPC title
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Frequently asked questions
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- What does patent US12190842B2 cover?
- A first flipflop outputs a first signal synchronized with a first clock signal. In the first transistor, the first clock signal is input to a first terminal and the second signal is output from a second terminal. In the fourth transistor, a first signal is input to a first terminal and a second terminal is electrically connected to a gate of the first transistor. In the sixth transistor, the th…
- Who is the assignee on this patent?
- Semiconductor Energy Lab
- What technology area does this patent fall under?
- Primary CPC classification G09G3/20. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Jan 07 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).