Display device including at least six transistors

Patent metadata

Field	Value
Publication number	US-9245891-B2
Application number	US-201314072878-A
Country	US
Kind code	B2
Filing date	Nov 6, 2013
Priority date	Sep 29, 2006
Publication date	Jan 26, 2016
Grant date	Jan 26, 2016

Abstract

By applying an AC pulse to a gate of a transistor which easily deteriorates, a shift in threshold voltage of the transistor is suppressed. However, in a case where amorphous silicon is used for a semiconductor layer of a transistor, the occurrence of a shift in threshold voltage naturally becomes a problem for a transistor which constitutes a part of circuit that generates an AC pulse. A shift in threshold voltage of a transistor which easily deteriorates and a shift in threshold voltage of a turned-on transistor are suppressed by signal input to a gate electrode of the transistor which easily deteriorates through the turned-on transistor. In other words, a structure for applying an AC pulse to a gate electrode of a transistor which easily deteriorates through a transistor to a gate electrode of which a high potential (VDD) is applied, is included.

First claim

What is claimed is:

1. A semiconductor device comprising: a first transistor; a second transistor; a third transistor; a fourth transistor; a fifth transistor; and a sixth transistor,
wherein one of a source and a drain of the first transistor is electrically connected to a first wiring,
wherein the other of the source and the drain of the first transistor is electrically connected to a second wiring,
wherein one of a source and a drain of the second transistor is electrically connected to a third wiring,
wherein the other of the source and the drain of the second transistor is electrically connected to the second wiring,
wherein one of a source and a drain of the third transistor is electrically connected to a fourth wiring,
wherein the other of the source and the drain of the third transistor is electrically connected to a gate of the sixth transistor,
wherein one of a source and a drain of the fourth transistor is electrically connected to the third wiring,
wherein the other of the source and the drain of the fourth transistor is electrically connected to the gate of the sixth transistor,
wherein one of a source and a drain of the fifth transistor is electrically connected to a gate of the first transistor,
wherein a gate of the fifth transistor is electrically connected to a fifth wiring,
wherein one of a source and a drain of the sixth transistor is electrically connected to the third wiring,
wherein the other of the source and the drain of the sixth transistor is electrically connected to the gate of the first transistor,
wherein the gate of the sixth transistor is electrically connected to a sixth wiring, and
wherein a ratio W/L of a channel width W to a channel length L of the fourth transistor is higher than a ratio W/L of the third transistor.

2. The semiconductor device according to claim 1 , wherein a gate of the fourth transistor is electrically connected to the fifth wiring.

3. The semiconductor device according to claim 1 , wherein a gate of the fourth transistor is electrically connected to the gate of the first transistor.

4. The semiconductor device according to claim 1 , wherein a gate of the second transistor is electrically connected to a seventh wiring.

5. The semiconductor device according to claim 1 , wherein a gate of the second transistor is electrically connected to the other of the source and the drain of the third transistor and the other of the source and the drain of the fourth transistor.

6. The semiconductor device according to claim 1 , wherein the other of the source and the drain of the fifth transistor is electrically connected to the fifth wiring.

7. The semiconductor device according to claim 1 , wherein the other of the source and the drain of the fifth transistor is electrically connected to an eighth wiring.

8. The semiconductor device according to claim 1 , wherein one of the first to sixth transistors comprises an oxide semiconductor.

9. The semiconductor device according to claim 1 , wherein a clock signal is input to the fourth wiring.

10. The semiconductor device according to claim 1 ,
wherein the one of the source and the drain of the first transistor is directly connected to the first wiring,
wherein the other of the source and the drain of the first transistor is directly connected to the second wiring,
wherein the one of the source and the drain of the second transistor is directly connected to the third wiring,
wherein the other of the source and the drain of the second transistor is directly connected to the second wiring,
wherein the one of the source and the drain of the third transistor is directly connected to the fourth wiring,
wherein the other of the source and the drain of the third transistor is directly connected to the gate of the sixth transistor,
wherein the one of the source and the drain of the fourth transistor is directly connected to the third wiring,
wherein the other of the source and the drain of the fourth transistor is directly connected to the gate of the sixth transistor,
wherein the one of the source and the drain of the fifth transistor is directly connected to the gate of the first transistor,
wherein the gate of the fifth transistor is directly connected to the fifth wiring,
wherein the one of the source and the drain of the sixth transistor is directly connected to the third wiring,
wherein the other of the source and the drain of the sixth transistor is directly connected to the gate of the first transistor, and
wherein the gate of the sixth transistor is directly connected to the sixth wiring.

11. A semiconductor device comprising: a first transistor; a second transistor; a third transistor; a fourth transistor; a fifth transistor; a sixth transistor; and a seventh transistor,
wherein one of a source and a drain of the first transistor is electrically connected to a first wiring,
wherein the other of the source and the drain of the first transistor is electrically connected to a second wiring,
wherein one of a source and a drain of the second transistor is electrically connected to a third wiring,
wherein the other of the source and the drain of the second transistor is electrically connected to the second wiring,
wherein one of a source and a drain of the third transistor is electrically connected to a fourth wiring,
wherein the other of the source and the drain of the third transistor is electrically connected to a gate of the sixth transistor,
wherein one of a source and a drain of the fourth transistor is electrically connected to the third wiring,
wherein the other of the source and the drain of the fourth transistor is electrically connected to the gate of the sixth transistor,
wherein one of a source and a drain of the fifth transistor is electrically connected to a gate of the first transistor,
wherein a gate of the fifth transistor is electrically connected to a fifth wiring,
wherein one of a source and a drain of the sixth transistor is electrically connected to the third wiring,
wherein the other of the source and the drain of the sixth transistor is electrically connected to the gate of the first transistor,
wherein one of a source and a drain of the seventh transistor is electrically connected to the third wiring,
wherein the other of the source and the drain of the seventh transistor is electrically connected to the gate of the first transistor,
wherein a gate of the seventh transistor is electrically connected to a sixth wiring, and
wherein a ratio W/L of a channel width W to a channel length L of the fourth transistor is higher than a ratio W/L of the third transistor.

12. The semiconductor device according to claim 11 , wherein a gate of the fourth transistor is electrically connected to the fifth wiring.

13. The semiconductor device according to claim 11 , wherein a gate of the fourth transistor is electrically connected to the gate of the first transistor.

14. The semiconductor device according to claim 11 , wherein a gate of the second transistor is electrically connected to a seventh wiring.

15. The semiconductor device according to claim 11 , wherein a gate of the second transistor is electrically connected to the other of the source and the drain of the third transistor and the other of the source and the drain of the fourth transistor.

16. The semiconductor device according to claim 11 , wherein the other of the source and the drain of the fifth transistor is electrically connected to the fifth wiring.

17. The semiconductor device according to claim 11 , wherein the other of the source and the drain of the fifth

Assignees

• Semiconductor Energy Lab

Inventors

• Umezaki Atsushi

Classifications

• H01H71/10

  Operating or release mechanisms · CPC title

• H01H71/02

  Housings; Casings; Bases; Mountings · CPC title

• G02F1/13454

  Drivers integrated on the active matrix substrate (G02F1/136277 takes precedence) · CPC title

• G02F1/13624

  having more than one switching element per pixel · CPC title

• G09G2300/0417

  Special arrangements specific to the use of low carrier mobility technology · CPC title