Display panel and display panel driving method

Patent metadata

Field	Value
Publication number	US-12190806-B2
Application number	US-202218083328-A
Country	US
Kind code	B2
Filing date	Dec 16, 2022
Priority date	Sep 9, 2022
Publication date	Jan 7, 2025
Grant date	Jan 7, 2025

Abstract

A display panel including a pixel circuit and a light-emitting element, the pixel circuit including a driving transistor, a data writing transistor, a threshold compensation transistor, a first reset transistor, a bias transistor, and a light-emitting control module, the data writing transistor being electrically connected to a first terminal of the driving transistor, the threshold compensation transistor being connected in series between a gate of the driving transistor and a second terminal of the driving transistor, and configured to detect and self-compensate a threshold voltage deviation of the driving transistor, the first reset transistor and the bias transistor being electrically connected to the second terminal of the driving transistor, the light-emitting control module being connected in series with the driving transistor and the light-emitting element to control whether a driving current flows through the light-emitting element, the data writing transistor and the first reset transistor having the same transistor type.

First claim

What is claimed is:

1. A display panel comprising:
a pixel circuit, the pixel circuit including a driving transistor, a data writing transistor, a threshold compensation transistor, a first reset transistor, a bias transistor, and a light-emitting control module; and
a light-emitting element, wherein:
the data writing transistor is electrically connected to a first terminal of the driving transistor;
the threshold compensation transistor is connected in series between a gate of the driving transistor and a second terminal of the driving transistor, and configured to detect and self-compensate a threshold voltage deviation of the driving transistor;
the first reset transistor is electrically connected to the second terminal of the driving transistor;
the bias transistor is electrically connected to the second terminal of the driving transistor, wherein the first reset transistor and the bias transistor are different transistors, and the bias transistor receives an existing high-level signal in the display panel for biasing the second terminal of the driving transistor without requiring an independent shift register circuit to provide a biasing signal;
the light-emitting control module is connected in series with the driving transistor and the light-emitting element to control whether a driving current flows through the light-emitting element; and
the data writing transistor and the first reset transistor have the same transistor type.

2. The display panel of claim 1 , wherein:
the data writing transistor and the first reset transistor are P-type transistors.

3. The display panel of claim 1 , wherein:
a gate of the data writing transistor is electrically connected to a first scan signal terminal;
a gate of the first reset transistor is electrically connected to a second scan signal terminal; and
for the pixel circuits located in adjacent rows, a signal of the second scan signal terminal to which the gate of the first reset transistor of the pixel circuit in a current row is electrically connected is the same as a signal of the first scan signal terminal to which the gate of the data writing transistor of the pixel circuit located in a previous row is electrically connected to.

4. The display panel of claim 1 , wherein:
a gate of the bias transistor is electrically connected to a third scan signal terminal;
the pixel circuit further includes a second reset transistor, a first terminal of the second reset transistor being electrically connected to a second reference voltage terminal, a second terminal of the second reset transistor being electrically connected to the light-emitting element, a gate of the second reset transistor being electrically connected to a fourth scan signal terminal; and
a signal provided by the third scan signal terminal is the same as a signal provided by the fourth scan signal terminal connected to the same pixel circuit.

5. The display panel of claim 1 , wherein:
a gate of the bias transistor is electrically connected to a third scan signal terminal;
the pixel circuit further includes a second reset transistor, a first terminal of the second reset transistor being electrically connected to a second reference voltage terminal, a second terminal of the second reset transistor being electrically connected to the light-emitting element, a gate of the second reset transistor being electrically connected to a fourth scan signal terminal; and
for pixel circuits located in two adjacent groups, a signal of the third scan signal terminal to which the gate of the bias transistor of the pixel circuit in a current group is electrically connected is the same as a signal of the fourth scan signal terminal to which the gate of the second reset transistor of the pixel circuit located in a previous group is electrically connected to, one group including two adjacent rows of pixel circuits.

6. The display panel of claim 1 , wherein:
an active layer of the threshold compensation transistor includes metal oxide.

7. The display panel of claim 1 , wherein:
the pixel circuit further includes a second reset transistor;
the gate of the driving transistor is electrically connected to a first node, the first terminal of the driving transistor is electrically connected to a second node, the second terminal of the driving transistor is electrically connected to a third node;
a gate of the data writing transistor is electrically connected to a first scan signal terminal, a first terminal of the data writing transistor is electrically connected to a data signal terminal, and a second terminal of the data writing transistor is electrically connected to the second node;
a gate of the first reset transistor is electrically connected to a second scan signal terminal, a first terminal of the first reset transistor is electrically connected to a first reference voltage terminal, a second terminal of the first reset transistor is electrically connected to the third node;
a gate of the bias transistor is electrically connected to a third scan signal terminal, a first terminal of the bias transistor is electrically connected to a bias voltage terminal, and a second terminal of the bias transistor is electrically connected to the third node;
a gate of the threshold compensation transistor is electrically connected to a fifth scan signal terminal, a first terminal of the threshold compensation transistor is electrically connected to the third node, and a second terminal of the threshold compensation transistor is electrically connected to the first node;
a gate of the second reset transistor is electrically connected to a fourth scan signal terminal, a first terminal of the second reset transistor is electrically connected to a second reference voltage terminal, and a second terminal of the second reset transistor is electrically connected to a fourth node;
the light-emitting control module includes a first light-emitting control transistor and a second light-emitting control transistor, the first light-emitting control transistor being electrically connected to the second node, a first terminal of the second light-emitting control transistor being electrically connected to the third node, a second terminal of the second light-emitting control transistor being electrically connected to the fourth node, a gate of the first light-emitting control transistor and a gate of the second light-emitting control transistor being electrically connected to a light-emitting control signal terminal; and
the light-emitting element is electrically connected to the fourth node.

8. The display panel of claim 1 further comprising:
a first scan circuit, a second scan circuit, a third scan circuit, and a light emission control circuit, the first scan circuit, the second scan circuit, the third scan circuit, and the light emission control circuit including a multi-stage cascaded shift register respectively, wherein:
a control signal of the data writing transistor and a control signal of the first reset transistor are provided by the first scan circuit;
a control signal of the threshold compensation transistor is provided by the second scan circuit;
a control signal of the bias transistor is provided by the third scan circuit; and
the light-emitting control module includes a first light-emitting control transistor and a second light-emitting control transistor, control signals of the first light-emitting control transistor and the second light-emitting control transistor being provided by the light emission control circuit.

9. The display panel of claim 8 , wherein:
the shift register included in the first scan circuit is a first shift register, a stage of the first shift register being configured to provide the control signal for the da

Assignees

• Xiamen Tianma Display Tech Co Ltd

Inventors

• He Shui
• Zheng Shanshan
• Yang Jinjin
• Zhong Jiansheng
• Zhong Qiaoling

Classifications

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2310/061

  for resetting or blanking · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G2300/0861

  with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes · CPC title

• G09G2300/0819

  used for counteracting undesired variations, e.g. feedback or autozeroing · CPC title