Data locality enhancement for graphics processing units

Patent metadata

Field	Value
Publication number	US-12190118-B2
Application number	US-202318339454-A
Country	US
Kind code	B2
Filing date	Jun 22, 2023
Priority date	Nov 15, 2019
Publication date	Jan 7, 2025
Grant date	Jan 7, 2025

Abstract

Embodiments described herein provide an apparatus comprising a plurality of processing resources including a first processing resource and a second processing resource, a memory communicatively coupled to the first processing resource and the second processing resource, and a processor to receive data dependencies for one or more tasks comprising one or more producer tasks executing on the first processing resource and one or more consumer tasks executing on the second processing resource and move a data output from one or more producer tasks executing on the first processing resource to a cache memory communicatively coupled to the second processing resource. Other embodiments may be described and claimed.

First claim

What is claimed is:

1. An apparatus comprising:
processor circuitry coupled to a memory, the processor circuitry to:
map one or more tasks to one or more processing resources; and
forward one or more destination identifiers corresponding to the one or more tasks to the one or more processing resources, wherein the one or more tasks are represented in a task graph, and receive data dependencies associated with the one or more tasks including one or more producer tasks or one or more consumer tasks.

2. The apparatus of claim 1 , wherein the one or more processing resources comprise one or more of a first processing resource or a second processing resource.

3. The apparatus of claim 1 , wherein the one or more producer tasks execute on the first processing resource, and wherein the one or more consumer tasks execute on the second processing resource.

4. The apparatus of claim 3 , wherein the processor circuitry is further to transport a data output from the one or more producer tasks executing on the first processing resource to a cache memory communicatively coupled to the second processing resource.

5. The apparatus of claim 3 , wherein the processing circuitry is further to enqueue a kernel for execution by the one of the processing resources, wherein the cache memory comprises a L1 cache, and wherein the L1 cache is shared between the first and second processing resources.

6. The apparatus of claim 1 , wherein the processor circuitry comprises graphics processor circuitry co-located with application processor circuitry on a semiconductor package.

7. A method comprising:
mapping, by a processor of a computing device, one or more tasks to one or more processing resources; and
forwarding one or more destination identifiers corresponding to the one or more tasks to the one or more processing resources, wherein the one or more tasks are represented in a task graph, and receiving data dependencies associated with the one or more tasks including one or more producer tasks or one or more consumer tasks.

8. The method of claim 7 , wherein the one or more processing resources comprise one or more of a first processing resource or a second processing resource.

9. The method of claim 7 , wherein the one or more producer tasks execute on the first processing resource, and wherein the one or more consumer tasks execute on the second processing resource.

10. The method of claim 9 , further comprising transporting a data output from the one or more producer tasks executing on the first processing resource to a cache memory communicatively coupled to the second processing resource.

11. The method of claim 9 , further comprising enqueuing a kernel for execution by one of the processing resources, wherein the cache memory comprises a L1 cache, and wherein the L1 cache is shared between the first and second processing resources.

12. The method of claim 7 , wherein the processor is coupled to a memory, the processor comprises a graphics processor co-located with an application processor on a semiconductor package.

13. At least one computer-readable medium having stored thereon instructions which, when executed, cause a computing device to facilitate operations comprising:
mapping one or more tasks to one or more processing resources; and
forwarding one or more destination identifiers corresponding to the one or more tasks to the one or more processing resources, wherein the one or more tasks are represented in a task graph, and receiving data dependencies associated with the one or more tasks including one or more producer tasks or one or more consumer tasks.

14. The computer-readable medium of claim 13 , wherein the one or more processing resources comprise one or more of a first processing resource or a second processing resource.

15. The computer-readable medium of claim 13 , wherein the one or more producer tasks execute on the first processing resource, and wherein the one or more consumer tasks execute on the second processing resource.

16. The computer-readable medium of claim 15 , wherein the operations further comprise transporting a data output from the one or more producer tasks executing on the first processing resource to a cache memory communicatively coupled to the second processing resource.

17. The computer-readable medium of claim 15 , wherein the operations further comprise enqueuing a kernel for execution by one of the processing resources, wherein the cache memory comprises a L1 cache, and wherein the L1 cache is shared between the first and second processing resources.

18. The computer-readable medium of claim 13 , wherein the computing device comprises one or more processors coupled to a memory, the one or more processors include one or more graphics processors co-located with one or more application processors on a semiconductor package.

Assignees

• Intel Corp

Inventors

• Hughes Christopher J
• Surti Prasoonkumar
• Lueh Guei-Yuan
• Lake Adam T
• Boyce Jill
• Maiyuran Subramaniam
• Xu Lidong
• Holland James M
• Ranganathan Vasanth
• Kaburlasos Nikos
• Koker Altug
• Appu Abhishek R

Classifications

• G06N3/09

  Supervised learning · CPC title

• G06N3/0495

  Quantised networks; Sparse networks; Compressed networks · CPC title

• G06N3/0464

  Convolutional networks [CNN, ConvNet] · CPC title

• G06N3/0895

  Weakly supervised learning, e.g. semi-supervised or self-supervised learning · CPC title

• G06N3/0442

  characterised by memory or gating, e.g. long short-term memory [LSTM] or gated recurrent units [GRU] · CPC title