Semiconductor memory device

Patent metadata

Field	Value
Publication number	US-12185528-B2
Application number	US-202418403817-A
Country	US
Kind code	B2
Filing date	Jan 4, 2024
Priority date	Nov 30, 2020
Publication date	Dec 31, 2024
Grant date	Dec 31, 2024

Abstract

A semiconductor memory device includes a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, a boundary element isolation layer in the boundary region, the boundary element isolation layer being in a boundary element isolation recess and including first and second boundary liner layers extending along a profile of the boundary element isolation recess and a first gate structure on the core region and at least a part of the boundary element isolation layer, wherein the first gate structure includes a first high dielectric layer, and a first gate insulating pattern below the first high dielectric layer, with a top surface of the substrate being a base reference level, the first gate insulating pattern does not overlap a top surface of the first boundary liner layer, and wherein the first gate insulating pattern includes a first_1 gate insulating pattern between a top surface of the second boundary liner layer and a bottom surface of the first high dielectric layer, and a first_2 gate insulating pattern disposed a top surface of the core region and a bottom surface of the first high dielectric layer.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
a substrate including a cell region, a core region, and a boundary region between the cell region and the core region;
a word line structure buried in the substrate of the cell region;
a cell buffer layer on the word line structure, wherein the cell buffer layer includes a first insulating layer, a second insulating layer, and a third insulating layer that are stacked sequentially;
a boundary element isolation layer in the substrate of the boundary region, the boundary element isolation layer being in a boundary element isolation recess and including first and second boundary liner layers and a boundary element isolation filling layer; and
a first gate structure on the core region and at least a part of the boundary element isolation layer,
wherein the first boundary liner layer extends along a bottom surface of the boundary element isolation recess and sidewalls of the boundary element isolation recess,
wherein the second boundary liner layer extends on the first boundary liner layer, and comprises silicon nitride,
wherein the boundary element isolation filling layer is disposed on the second boundary liner layer,
wherein the first gate structure includes a first high dielectric layer, a first gate insulating pattern below the first high dielectric layer, and a first gate conductive pattern on the first high dielectric layer, with a top surface of the substrate being a base reference level,
wherein the second boundary liner layer protrudes from a top surface of the first boundary liner layer and a top surface of the boundary element isolation filling layer,
wherein a top surface of the word line structure and a topmost surface of the boundary element isolation filling layer are on the same plane,
wherein at least a part of the second boundary liner layer overlaps the first gate structure in a direction parallel to the top surface of the substrate,
wherein the first insulating layer and the third insulating layer comprise silicon oxide,
wherein the second insulating layer comprises silicon nitride, and
wherein based on the top surface of the substrate, a level of a top surface of the cell buffer layer is lower than a level of a top surface of the first gate conductive pattern.

2. The semiconductor memory device of claim 1 , wherein the first gate insulating pattern includes a first_1 gate insulating pattern between a top surface of the second boundary liner layer and a bottom surface of the first high dielectric layer, and a first_2 gate insulating pattern between a top surface of the substrate of the core region and a bottom surface of the first high dielectric layer.

3. The semiconductor memory device of claim 1 , wherein the first gate insulating pattern does not overlap the boundary element isolation filling layer in a direction perpendicular to the top surface of the substrate.

4. The semiconductor memory device of claim 3 , wherein the first high dielectric layer is in physical contact with the boundary element isolation filling layer.

5. The semiconductor memory device of claim 1 , wherein the first high dielectric layer overlaps the boundary element isolation layer and the substrate of the core region in a direction perpendicular to the top surface of the substrate.

6. The semiconductor memory device of claim 1 , wherein the first high dielectric layer is in physical contact with the first boundary liner layer.

7. The semiconductor memory device of claim 1 , wherein at least a part of the first gate structure overlaps the word line structure in the direction parallel to the top surface of the substrate.

8. A semiconductor memory device comprising: a substrate including a cell region, a core region, and a boundary region between the cell region and the core region; a word line structure buried in the substrate of the cell region; a cell buffer layer on the word line structure, wherein the cell buffer layer includes a first insulating layer, a second insulating layer, and a third insulating layer that are stacked sequentially; a boundary element isolation layer in the substrate of the boundary region; a first gate structure on the core region and at least a part of the boundary element isolation layer; a core element isolation layer in the core region, the core element isolation layer being in a core element isolation recess and including first and second core liner layers and a core element isolation filling layer; and a second gate structure on the core region and at least a part of the core element isolation layer, wherein the first gate structure does not overlap the substrate of the cell region in a direction perpendicular to the top surface of the substrate, wherein the first core boundary liner layer extends along a bottom surface of the element isolation recess and sidewalls of the core element isolation recess, wherein the second core boundary liner layer on the first core boundary liner layer, and comprises silicon nitride, wherein the core element isolation filling layer is disposed on the second boundary liner layer, wherein the first gate structure includes a first high dielectric layer, a first gate insulating pattern below the first high dielectric layer, and a first gate conductive pattern on the first high dielectric layer, with a top surface of the substrate being a base reference level, wherein the second gate structure includes a second high dielectric layer and a second gate insulating pattern below the second high dielectric layer with the top surface of the substrate being the base reference level, wherein a top surface of the word line structure and a topmost surface of the boundary element isolation filling layer are on the same plane, wherein the second boundary liner layer protrudes from a top surface of the first boundary liner layer and a top surface of the boundary element isolation filling layer, wherein the second core liner layer protrudes from a top surface of the first core liner layer and a top surface of the core element isolation filling layer, wherein the second gate insulating pattern is disposed between the second high dielectric layer and the second core liner layer, and wherein the second gate insulating pattern is not disposed between the second high dielectric layer and the first core liner layer.

9. The semiconductor memory device of claim 8 , wherein the second gate insulating pattern is not disposed between the second high dielectric layer and the core element isolation filling layer.

10. The semiconductor memory device of claim 8 , wherein the first insulating layer and the third insulating layer comprise silicon oxide,
wherein the second insulating layer comprises silicon nitride, and
wherein based on the top surface of the substrate, a level of a top surface of the cell buffer layer is lower than a level of a top surface of the first gate conductive pattern.

11. The semiconductor memory device of claim 8 , wherein the second boundary liner layer overlaps the second gate structure in a direction parallel to the top surface of the substrate.

12. The semiconductor memory device of claim 8 , wherein the first gate insulating pattern does not overlap a top surface of the first boundary liner layer, and overlaps a top surface of the second boundary liner layer and the top surface of the core region in the direction perpendicular to the top surface of the substrate.

13. The semiconductor memory device of claim 8 , wherein the second high dielectric layer is in physical contact with the core element isolation filling layer.

14. The semiconductor memory device of claim 8 , wherein the second high dielectric layer is in ph

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Dong Oh
• Kil Gyu Hyun
• Han Jung Hoon
• Back Doo San

Classifications

• H10B12/315 Primary

  with the capacitor higher than a bit line · CPC title

• H10B12/34 Primary

  the transistor being at least partially in a trench in the substrate · CPC title

• H10B12/50 Primary

  Peripheral circuit region structures · CPC title

• H10B12/05

  Making the transistor · CPC title