Method for forming capacitor via

Patent metadata

Field	Value
Publication number	US-12183776-B2
Application number	US-202117509167-A
Country	US
Kind code	B2
Filing date	Oct 25, 2021
Priority date	Jul 30, 2021
Publication date	Dec 31, 2024
Grant date	Dec 31, 2024

Abstract

A method for forming a capacitor via includes: providing a to-be-processed wafer, the to-be-processed wafer including a substrate and a first dielectric layer and a first mask layer that are sequentially formed on a surface of the substrate; etching the first mask layer according to a compensated first etching parameter, to form a first patterned layer extending in a first etching direction; sequentially forming a second dielectric layer and a second mask layer on a surface of the first patterned layer; etching the second mask layer and the second dielectric layer according to a compensated second etching parameter, to form a second patterned layer extending in a second etching direction; and etching the first dielectric layer with the first patterned layer and the second patterned layer together as a capacitor pattern, to form a capacitor via.

First claim

The invention claimed is:

1. A method for forming a capacitor via, comprising:
providing a to-be-processed wafer, the to-be-processed wafer comprising a substrate, and a first dielectric layer and a first mask layer that are sequentially formed on a surface of the substrate;
forming a photoresist layer on a surface of the first mask layer;
etching the photoresist layer in a vertical direction according to a compensated first etching parameter to form a patterned photoresist layer extending in a first etching direction;
etching the first mask layer with the patterned photoresist layer as a mask to form the first patterned layer;
sequentially forming a second dielectric layer and a second mask layer on a surface of the first patterned layer;
etching the second mask layer and the second dielectric layer according to a compensated second etching parameter to form a second patterned layer extending in a second etching direction; and
etching the first dielectric layer with the first patterned layer and the second patterned layer together as a capacitor pattern, to form a capacitor via.

2. The method according to claim 1 , wherein
a capacitor contact structure is provided in the substrate, and the capacitor via is butted with the capacitor contact structure.

3. The method according to claim 1 , further comprising:
compensating for the first etching parameter and the second etching parameter of the to-be-processed wafer with a preset deviation amount parameter to obtain the compensated first etching parameter and the compensated second etching parameter.

4. The method according to claim 3 , wherein
the etching the second mask layer and the second dielectric layer according to the compensated second etching parameter to form the second patterned layer extending in the second etching direction comprises:
etching the second mask layer in a vertical direction with the compensated second etching parameter, and continuously etching the second dielectric layer in the vertical direction to form the second patterned layer extending in the second etching direction.

5. The method according to claim 3 , further comprising:
acquiring an edge deviation amount parameter of a wafer sample and a machine deviation amount parameter at a radio frequency (RF) final stage; and
determining the preset deviation amount parameter according to the edge deviation amount parameter of the wafer sample and the machine deviation amount parameter.

6. The method according to claim 5 , wherein
the determining the preset deviation amount parameter according to the edge deviation amount parameter of the wafer sample and the machine deviation amount parameter comprises:
determining an adjusted deviation amount value according to an RF period and a current time;
determining a calculated deviation amount value by using a preset calculation model according to the edge deviation amount parameter of the wafer sample and the machine deviation amount parameter; and
correcting the calculated deviation amount value with the adjusted deviation amount value to obtain the preset deviation amount parameter.

7. The method according to claim 3 , wherein
the to-be-processed wafer comprises a plurality of edge exposure units, wherein the edge exposure units respectively correspond to different preset deviation amount parameters;
the method further comprises:
determining a target deviation amount parameter corresponding to a target edge exposure unit of the to-be-processed wafer, the target deviation amount parameter comprising a first target deviation amount parameter and a second target deviation amount parameter; and
wherein the compensating for the first etching parameter and the second etching parameter of the to-be-processed wafer with the preset deviation amount parameter to obtain the compensated first etching parameter and the compensated second etching parameter comprises:
compensating for a first etching parameter of the target edge exposure unit with the first target deviation amount parameter to obtain the compensated first etching parameter; and
compensating for a second etching parameter of the target edge exposure unit with the second target deviation amount parameter, to obtain the compensated second etching parameter.

8. The method according to claim 7 , further comprising:
acquiring a first edge deviation amount parameter corresponding to a target edge exposure unit of a wafer sample and a first machine deviation amount parameter in a horizontal direction at a RF final stage; and
determining the first target deviation amount parameter according to the first edge deviation amount parameter and the first machine deviation amount parameter; and
acquiring a second edge deviation amount parameter corresponding to the target edge exposure unit of the wafer sample and a second machine deviation amount parameter in a vertical direction at the RF final stage; and
determining the second target deviation amount parameter according to the second edge deviation amount parameter and the second machine deviation amount parameter.

9. The method according to claim 8 , further comprising:
randomly selecting n sampling points from the target edge exposure unit of the wafer sample;
determining first deviation amounts that respectively correspond to the n sampling points in the horizontal direction and second deviation amounts that respectively correspond to the n sampling points in the vertical direction;
determining the first edge deviation amount parameter corresponding to the target edge exposure unit of the wafer sample according to the first deviation amounts that respectively correspond to the n sampling points in the horizontal direction; and
determining the second edge deviation amount parameter corresponding to the target edge exposure unit of the wafer sample according to the second deviation amounts that respectively correspond to the n sampling points in the vertical direction.

10. The method according to claim 9 , wherein
the randomly selecting n sampling points from the target edge exposure unit of the wafer sample comprises:
slicing the target edge exposure unit of the wafer sample, to obtain a slice of the target edge exposure unit, the slice comprising the n sampling points, and each sampling point comprising a capacitor contact structure and a capacitor section.

11. The method according to claim 10 , wherein
the determining first deviation amounts that respectively correspond to the n sampling points in the horizontal direction comprises:
measuring a first positive distance and a first negative distance between a capacitor contact structure and a capacitor section in a first sampling point; and
calculating a first deviation amount of the first sampling point according to the first positive distance and the first negative distance of the first sampling point; and
the determining second deviation amounts that respectively correspond to the n sampling points in the vertical direction comprises:
measuring a second positive distance and a second negative distance between the capacitor contact structure and the capacitor section in the first sampling point; and
calculating a second deviation amount of the first sampling point according to the second positive distance and the second negative distance of the first sampling point,
wherein the first sampling point represents any sampling point in the n sampling points.

12. The method according to claim 11 , wherein
responding to the capacitor section does not deviate beyond an edge of the capacitor contact structure, the calculating the first deviation amount of the first sampling point and the second deviation amount of th

Assignees

• Changxin Memory Tech Inc

Inventors

• Wang Chunyang
• Li Zhenxing
• Shao Bo
• Liu Xinran

Classifications

• H10P74/203

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• H10P72/06

  Apparatus for monitoring, sorting, marking, testing or measuring · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10P76/2041 Primary

  Photolithographic processes · CPC title

• H10D1/68 Primary

  Capacitors having no potential barriers · CPC title