Array substrate, display apparatus, and method of fabricating array substrate

Patent metadata

Field	Value
Publication number	US-12183748-B2
Application number	US-202318518526-A
Country	US
Kind code	B2
Filing date	Nov 23, 2023
Priority date	Oct 12, 2019
Publication date	Dec 31, 2024
Grant date	Dec 31, 2024

Abstract

An array substrate including a display area having a plurality of subpixels is provided. The plurality of subpixels includes a plurality of first subpixels in a display-bonding sub-area and a plurality of second subpixels in a regular display sub-area. The array substrate includes a plurality of thin film transistors on a first side of the base substrate and respectively in the plurality of subpixels. A respective one of the plurality of first subpixels includes a bonding pad on a second side of a base substrate; a lead line electrically connecting a respective one of a plurality of thin film transistors to the bonding pad; and a via extending through the base substrate. The lead line is unexposed in the array substrate. The lead line extends from the first side to the second side of the base substrate through the via, to connect to the bonding pad.

First claim

What is claimed is:

1. An array substrate, comprising a display area having a plurality of subpixels;
wherein the display area comprises a regular display sub-area and a display-bonding sub-area;
the plurality of subpixels comprises a plurality of first subpixels in the display-bonding sub-area and a plurality of second subpixels in the regular display sub-area;
wherein the array substrate comprises:
a base substrate extending throughout the regular display sub-area and the display-bonding sub-area; and
a plurality of thin film transistors on a first side of the base substrate and respectively in the plurality of subpixels;
wherein a respective one of the plurality of first subpixels comprises:
a bonding pad on a second side of the base substrate, wherein the second side is opposite to the first side;
a lead line electrically connecting a respective one of the plurality of thin film transistors to the bonding pad, wherein the lead line is unexposed in the array substrate; and
a via extending through the base substrate;
wherein the lead line extends from the first side to the second side of the base substrate through the via, to connect to the bonding pad; and
the lead line is limited in the display-bonding sub-area, and/or the regular display sub-area abuts at least two sides of the display-bonding sub-area.

2. The array substrate of claim 1 , further comprising an insulating layer on the second side of the base substrate and limited in the display-bonding sub-area;
wherein the bonding pad is on a side of the insulating layer away from the base substrate; and
the via extends through the base substrate and the insulating layer.

3. The array substrate of claim 2 , wherein the base substrate has a first thickness t1 in a region corresponding to the bonding pad, and has a second thickness t2 in a region outside the region corresponding to the bonding pad;
the insulating layer has a third thickness t3; and
t 2>( t 1 +t 3).

4. The array substrate of claim 1 , further comprising a recess in a region corresponding to the bonding pad for bonding the bonding pad with an integrated circuit;
wherein the recess is on the second side of the base substrate, exposing a surface of the bonding pad.

5. The array substrate of claim 4 , further comprising an insulating layer on the second side of the base substrate and limited in the display-bonding sub-area;
wherein the bonding pad is on a side of the insulating layer away from the base substrate;
the via extends through the base substrate and the insulating layer; and
the recess exposes the surface of the bonding pad and a surface of the insulating layer.

6. The array substrate of claim 5 , wherein the base substrate has a first thickness t1 in a region corresponding to the bonding pad, and has a second thickness t2 in a region outside the region corresponding to the bonding pad;
the insulating layer has a third thickness t3;
the recess has a fourth thickness t4; and
t2 is substantially equal to a sum of t1, t3, and t4.

7. The array substrate of claim 2 , further comprising a plurality of additional insulating layers, each of which partially extending into the via.

8. The array substrate of claim 7 , wherein the plurality of additional insulating layers comprise a passivation layer extending throughout the display area;
wherein the passivation layer is on the first side of the base substrate, and at least partially covering a lateral side of the via; and
the lead line is on a side of the passivation layer away from the insulating layer.

9. The array substrate of claim 8 , wherein the plurality of additional insulating layers comprise further comprises a barrier layer extending throughout the display area;
wherein the barrier layer is on a side of the passivation layer and the lead line away from the base substrate; and
the insulating layer, the bonding pad, the passivation layer, and the barrier layer encapsulate the lead line inside the array substrate.

10. The array substrate of claim 9 , wherein the plurality of additional insulating layers comprise further comprises a buffer layer extending throughout the display area;
wherein the respective one of the plurality of thin film transistors comprises an active layer on a side of the buffer layer away from the base substrate.

11. The array substrate of claim 1 , wherein the base substrate is a flexible base substrate.

12. A display apparatus, comprising the array substrate of claim 1 , and one or more integrated circuits connected to the array substrate.

13. A method of fabricating an array substrate, comprising forming a display area having a plurality of subpixels;
wherein forming the display area comprises forming a regular display sub-area and forming a display-bonding sub-area;
forming the plurality of subpixels comprises forming a plurality of first subpixels in the display-bonding sub-area and forming a plurality of second subpixels in the regular display sub-area;
wherein the method comprises forming a base substrate extending throughout the regular display sub-area and the display-bonding sub-area; and
forming a plurality of thin film transistors on a first side of the base substrate and respectively in the plurality of subpixels;
wherein forming a respective one of the plurality of first subpixels comprises:
forming a bonding pad on a second side of the base substrate, wherein the second side is opposite to the first side;
forming a lead line electrically connecting a respective one of the plurality of thin film transistors to the bonding pad, wherein the lead line is unexposed in the array substrate; and
forming a via extending through the base substrate;
wherein the lead line is formed to extend from the first side to the second side of the base substrate through the via, to connect to the bonding pad; and
the lead line is limited in the display-bonding sub-area, and/or the regular display sub-area abuts at least two sides of the display-bonding sub-area.

14. The method of claim 13 , further comprising:
providing a support substrate;
forming a debonding layer limited in the display-bonding sub-area, and in a region corresponding to the bonding pad;
forming the bonding pad on a side of the debonding layer away from the support substrate;
forming an insulating material layer limited in the display-bonding sub-area;
forming a base substrate material layer throughout the regular display sub-area and the display-bonding sub-area, and on a side of the insulating material layer away from the support substrate; and
etching the insulating material layer and the base substrate material layer to form the via extending through the insulating material layer and the base substrate material layer to expose a contacting surface of the bonding pad, thereby forming an insulating layer limited in the display-bonding sub-area, and the base substrate on the insulating layer.

15. The method of claim 14 , further comprising forming a passivation material layer throughout the regular display sub-area and the display-bonding sub-area, and on a side of the base substrate away from the support substrate; and
etching the passivation material layer to expose the contacting surface of the bonding pad, thereby forming a passivation layer;
wherein the passivation layer is formed on the first side of the base substrate, and at least partially covering a lateral side of the via.

16. The method of claim 15 , further comprising forming the lead line of a side of the passivation layer away from the base substrate;
wherein the lead line is formed to extend into the

Assignees

• Boe Technology Group Co Ltd

Inventors

• Wang Ke
• Di Muxin
• Liang Zhiwei
• Wang Guoqiang
• Gu Renquan
• Song Xiaoxin
• Zhu Xiaoyan
• Liu Yingwei
• Cao Zhanfeng

Classifications

• H10D86/471

  having different architectures, e.g. having both top-gate and bottom-gate TFTs · CPC title

• H10D86/0221

  comprising manufacture, treatment or patterning of TFT semiconductor bodies · CPC title

• H10D86/441 Primary

  Interconnections, e.g. scanning lines · CPC title

• H10D86/60 Primary

  wherein the TFTs are in active matrices · CPC title

• H10D86/411

  characterised by materials, geometry or structure of the substrates · CPC title