Display device and semiconductor device

Patent metadata

Field	Value
Publication number	US-2021109412-A1
Application number	US-202017066493-A
Country	US
Kind code	A1
Filing date	Oct 9, 2020
Priority date	Oct 11, 2019
Publication date	Apr 15, 2021
Grant date	—

Abstract

According to one embodiment, a display device includes a semiconductor layer, a first insulating layer, a gate electrode, a second insulating layer and a plurality of transparent conductive layers. The transparent conductive layers include a pixel electrode, a first conductive layer and a second conductive layer. The pixel electrode is in contact with the second conductive layer. The second conductive layer is in contact with the first conductive layer. The first conductive layer is brought into contact with a second region of the semiconductor layer through a first contact hole.

First claim

What is claimed is:

1 . A display device comprising:
a semiconductor layer including a first region, a second region and a channel region between the first region and the second region; a first insulating layer located on the semiconductor layer; a gate electrode located on the first insulating layer and opposing the channel region; a second insulating layer located on the first insulating layer and the gate electrode; and a plurality of transparent conductive layers located above the second insulating layer, the plurality of transparent conductive layers each including a pixel electrode, a first conductive layer and a second conductive layer, the pixel electrode being in contact with the second conductive layer, the second conductive layer being in contact with the first conductive layer, the first conductive layer being in contact with the second region of the semiconductor layer through a first contact hole formed in the first insulating layer and the second insulating layer.

2 . The device of claim 1 , further comprising:
a plurality of gates lines extending in the first direction and arranged in a second direction intersecting the first direction, with intervals therebetween; and a plurality of source lines extending in the second direction and arranged in the first direction with intervals therebetween, to intersect the plurality of gates lines, wherein the gate electrode is electrically connected to one of the plurality of gate lines and is located in a region where a respective one of the plurality of gate lines and a respective one of the plurality of source lines overlap, the first region is electrically connected to one of the plurality of source lines, the first conductive layer is located in an open area surrounded by a respective adjacent pair of gate lines of the plurality of gate lines and a respective adjacent pair of source lines of the plurality of source lines, and a width of the open area in the second direction is less than a width of the gate line in the second direction.

3 . The device of claim 2 , wherein
the second region is located in the open area together with the first conductive layer, and the semiconductor layer is formed of an oxide semiconductor.

4 . The device of claim 3 , further comprising:
a third insulating layer located on the first conductive layer and the second insulating layer; a fourth insulating layer located on the third insulating layer; a fifth insulating layer located on the fourth insulating layer; and a sixth insulating layer located on the fifth insulating layer, wherein the plurality of transparent conductive layers further include a third conductive layer, a fourth conductive layer and a fifth conductive layer, the second conductive layer is provided on the third insulating layer, covered by the fourth insulating layer and brought into contact with the first conductive layer through a second contact hole formed in the third insulating layer, the third conductive layer is provided on the fourth insulating layer and covered by the fifth insulating layer, and opposes the second conductive layer, the fourth conductive layer is provided on the fifth insulating layer, covered by the sixth insulating layer and electrically connected to the second conductive layer, and opposes the third conductive layer, the fifth conductive layer is provided on the sixth insulating layer and electrically connected to the third conductive layer, and opposes the fourth conductive layer, the pixel electrode is configured by the fourth conductive layer, and the first conductive layer, the second conductive layer and the fourth conductive layer constitute a first electric system, which is electrically independent from a second electric system constituted by the third conductive layer and the fifth conductive layer.

5 . The device of claim 1 , further comprising:
a first substrate; a second substrate disposed to oppose the first substrate with a gap therebetween; and a liquid crystal layer held between the first substrate and the second substrate, wherein the first substrate includes the semiconductor layer, the first insulating layer, the gate electrode, the second insulating layer and the pixel electrode.

6 . A display device comprising:
a semiconductor layer including a first region, a second region and a channel region between the first region and the second region; a first insulating layer located on the semiconductor layer; a gate electrode located on the first insulating layer and opposing the channel region; a second insulating layer located on the first insulating layer and the gate electrode; and a pixel electrode located above the second insulating layer and electrically connected to the second region, the channel region being bent in a region overlapping the gate electrode.

7 . The device of claim 6 , further comprising:
a plurality of gates lines extending in the first direction and arranged in a second direction intersecting the first direction, with intervals therebetween; and a plurality of source lines extending in the second direction and arranged in the first direction with intervals therebetween, to intersect the plurality of gates lines, wherein the gate electrode is electrically connected to one of the plurality of gate lines and is located in a region where a respective one of the plurality of gate lines and a respective one of the plurality of source lines overlap, and the channel region is bent in a region where a respective one of the plurality of gate lines and a respective one of the plurality of source lines overlap each other.

8 . The device of claim 7 , further comprising
a first transparent conductive layer provided on the second insulating layer and brought into contact with the second region through a first contact hole formed in the first insulating layer and the second insulating layer, wherein the first transparent conductive layer is located in an open area surrounded by a respective adjacent pair of gate lines of the plurality of gate lines and a respective adjacent pair of source lines of the plurality of source lines, and the pixel electrode is electrically connected to the second region via the first transparent conductive layer.

9 . The device of claim 8 , wherein
the second region is located in the open area together with the first transparent conductive layer, and the semiconductor layer is formed of an oxide semiconductor.

10 . The device of claim 8 , further comprising:
a third insulating layer located on the second insulating layer and the first transparent conductive layer; and a second transparent conductive layer provided on the third insulating layer and brought into contact with the first transparent conductive layer through a second contact hole formed in the third insulating layer, wherein the pixel electrode is electrically connected to the second region via the first transparent conductive layer and the second transparent conductive layer, the third insulating layer includes a colored layer comprising a first flat surface on a side opposing the second transparent conductive layer, and an organic insulating layer located between the colored layer and the second transparent conductive layer and comprising a second flat surface brought into contact with the second transparent conductive layer, and in a direction parallel to the second flat surface, a second minimum distance from a central axis of the second contact hole to the second flat surface is less than a first minimum distance from the central axis of the second contact hole to the first flat surface.

11 . The device of claim 6 , further comprising:

Assignees

• Japan Display Inc

Inventors

• Suzumura Isao
• Kimura Fumiya
• Mochizuki Kazuhide
• Tanaka Hitoshi
• Akutsu Kenichi
• Shimada Atsuko

Classifications

• H10D30/674

  characterised by the active materials · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D86/423

  comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title