Hybrid metal line structure

Patent metadata

Field	Value
Publication number	US-12183671-B2
Application number	US-202318313480-A
Country	US
Kind code	B2
Filing date	May 8, 2023
Priority date	Mar 25, 2021
Publication date	Dec 31, 2024
Grant date	Dec 31, 2024

Abstract

The present disclosure relates to an integrated chip that includes a substrate, a first metal line, and a hybrid metal line. The first metal line includes a first metal material and is within a first interlayer dielectric (ILD) layer over the substrate. The hybrid metal line is also within the first ILD layer. The hybrid metal line includes a pair of first metal segments that comprise the first metal material. The hybrid metal line further includes a second metal segment that comprises a second metal material that is different from the first metal material. The second metal segment is laterally between the pair of first metal segments.

First claim

What is claimed is:

1. An integrated chip comprising:
a substrate;
a first metal line over the substrate, the first metal line comprising a first metal; and
a hybrid metal line over the substrate and laterally spaced from the first metal line by a first dielectric layer, the hybrid metal line comprising:
a second metal line comprising a second metal, different than the first metal; and
a third metal line and a fourth metal line on opposite sides of the second metal line and coupled to the second metal line, the third metal line and the fourth metal line comprising the first metal, wherein a bottom surface of the third metal line is spaced from a bottom surface of the fourth metal line.

2. The integrated chip of claim 1 , wherein the hybrid metal line has a first width along a bottom of the hybrid metal line and a second width, less than the first width, along a top of the hybrid metal line.

3. The integrated chip of claim 1 , wherein a cavity is within the first dielectric layer and directly between the first metal line and the hybrid metal line.

4. The integrated chip of claim 1 , further comprising:
a first metal liner disposed along sidewalls and a lower surface of the second metal line, wherein the first metal liner is directly between the second metal line and the third metal line, and wherein the first metal liner is directly between the second metal line and the fourth metal line.

5. The integrated chip of claim 4 , wherein the first metal liner extends directly between the bottom surface of the third metal line and the bottom surface of the fourth metal line.

6. The integrated chip of claim 1 , wherein the second metal line extends directly between the bottom surface of the third metal line and the bottom surface of the fourth metal line.

7. The integrated chip of claim 1 , wherein the bottom surface of the third metal line and the bottom surface of the fourth metal line are above a bottom surface of the second metal line.

8. The integrated chip of claim 1 , further comprising:
an adhesion layer disposed along the bottom surface of the third metal line and the bottom surface of the fourth metal line.

9. The integrated chip of claim 1 , wherein the first dielectric layer comprises a first dielectric and a second dielectric, and wherein the first dielectric is on opposite sides of the second dielectric.

10. An integrated chip comprising:
a substrate;
a first metal line over the substrate, the first metal line comprising a first metal;
a first dielectric layer over the substrate and beside the first metal line; and
a hybrid metal line over the substrate and laterally spaced from the first metal line by the first dielectric layer, the hybrid metal line comprising:
a first metal segment comprising a second metal, different from the first metal;
a second metal segment on a first side of the first metal segment, the second metal segment comprising the first metal, wherein a top surface of the second metal segment has a first width and a bottom surface of the second metal segment has a second width; and
a third metal segment on a second side of the first metal segment, opposite the first side, the third metal segment comprising the first metal, wherein a top surface of the third metal segment has a third width, greater than the first width, and a bottom surface of the third metal segment has a fourth width, greater than the second width.

11. The integrated chip of claim 10 , wherein the bottom surface of the second metal segment is spaced from the bottom surface of the third metal segment.

12. The integrated chip of claim 11 , wherein a bottom surface of the first metal segment is directly between the bottom surface of the second metal segment and the bottom surface of the third metal segment.

13. The integrated chip of claim 10 , the hybrid metal line further comprising:
a fourth metal segment directly between the second metal segment and the first metal segment, the fourth metal segment comprising a third metal, different from the first metal and the second metal; and
a fifth metal segment directly between the third metal segment and the first metal segment, the fifth metal segment comprising the third metal.

14. The integrated chip of claim 13 , wherein the fourth metal segment extends directly between the bottom surface of the second metal segment and a bottom surface of the first metal segment, and wherein the fifth metal segment extends directly between the bottom surface of the third metal segment and the bottom surface of the first metal segment.

15. The integrated chip of claim 14 , wherein the first metal segment extends directly between a bottom surface of the fourth metal segment and a bottom surface of the fifth metal segment.

16. The integrated chip of claim 10 , wherein a top surface of the first metal segment has a fifth width and a bottom surface of the first metal segment has a sixth width, wherein a sum of the first width, the third width, and the fifth width is less than a sum of the second width, the fourth width, and the sixth width.

17. An integrated chip comprising:
a substrate;
a first dielectric layer over the substrate;
a first metal line over the substrate, the first metal line comprising a first metal; and
a hybrid metal line over the substrate, the first dielectric layer between the hybrid metal line and the first metal line, the hybrid metal line comprising:
a second metal line comprising a second metal, different than the first metal; and
a third metal line and a fourth metal line on opposite sides of the second metal line and coupled to the second metal line, the third metal line and the fourth metal line comprising the first metal,

wherein a width of the hybrid metal line along a bottom of the hybrid metal line is greater than a width of the hybrid metal line along a top of the hybrid metal line.

18. The integrated chip of claim 17 , wherein a bottom surface of the second metal line has a first width and a top surface of the second metal line has a second width, greater than the first width, wherein a bottom surface of the third metal line has a third width and a top surface of the third metal line has a fourth width, less than the third width, and wherein a bottom surface of the fourth metal line has a fifth width and a top surface of the fourth metal line has a sixth width, less than the fifth width.

19. The integrated chip of claim 17 , wherein a distance between an outer sidewall of the third metal line and an outer sidewall of the fourth metal line along top surfaces of the third metal line and the fourth metal line is less than a distance between the outer sidewall of the third metal line and the outer sidewall of the fourth metal line along bottom surfaces of the third metal line and the fourth metal line.

20. The integrated chip of claim 17 , wherein a bottom surface of the third metal line has a first width and a bottom surface of the fourth metal line has a second width, greater than the first width.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Ho Pokuan
• Wu Chia-Tien
• Chen Hsin-Ping
• Chu Wei-Chen

Classifications

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/0633

  using subtractive patterning of the conductive members · CPC title

• H10W20/438

  Interconnections with multiple fill metals, e.g. having different metals in wide and narrow interconnections, or having different metals in vias and in trenches · CPC title