Processor peak current control apparatus and method

Patent metadata

Field	Value
Publication number	US-12181947-B2
Application number	US-202017030175-A
Country	US
Kind code	B2
Filing date	Sep 23, 2020
Priority date	Sep 23, 2020
Publication date	Dec 31, 2024
Grant date	Dec 31, 2024

Abstract

A driver (e.g., a firmware or software) that improves the performance of the system-on-chip (SoC) in battery mode. The driver is a Peak Power Manager (PPM) which allows drastically higher SoC peak power limit levels (and thus higher Turbo performance) in battery mode. The PPM sets the Vth threshold voltage (the voltage level at which the platform will throttle the SoC) in such a way as to prevent the system from unexpected shutdown (or black screening). The PPM calculates the Psoc,pk SoC Peak Power Limit (e.g., PL4), according to the threshold voltage (Vth). These are two dependent parameters, if one is set, the other can be calculated. The scheme by the PPM is used to optimally set one parameter (Vth) based on the system parameters, and the history of the operation.

First claim

What is claimed is:

1. A machine-readable storage media comprising machine- executable instructions that when executed cause one or more machines to perform a method comprising:
calculating a current threshold voltage as a function of battery no-load voltage, maximum threshold voltage, and a voltage gap between the battery no-load voltage and a previous threshold voltage;
calculating a processor peak power limit as part of a system peak power limit which in turn is a function of the current threshold voltage;
sending the current threshold voltage to a threshold circuitry; and
sending the processor peak power limit to the processor, wherein the current threshold sets a threshold voltage to trigger throttling of the processor to manage peak power of the processor.

2. The machine-readable storage media of claim 1 , wherein calculating the processor peak power limit comprises:
calculating a system peak power as a function of the current threshold voltage, battery no-load voltage, system power rail capacitance, time between system voltage drops below the current voltage threshold and the system reduces peak power, battery resistance, and a minimum voltage level of the system power rail.

3. The machine-readable storage media of claim 2 , wherein calculating the processor peak power limit comprises:
identifying a power value for non-processor loads supplied by a system supply, and scaling a difference between the system peak power and the identified power value.

4. The machine-readable storage media of claim 3 , wherein scaling the difference comprises accounting for power conversion loss of a voltage regulator.

5. The machine-readable storage media of claim 1 comprising machine- executable instructions that when executed cause the one or more machines to perform the method comprising:
comparing the processor peak power limit against a maximum power peak power limit; and
setting the processor peak power limit to the maximum processor peak power limit if the processor peak power limit is greater than the maximum power peak power limit.

6. The machine-readable storage media of claim 5 comprising machine-executable instructions that when executed cause the one or more machines to perform the method comprising:
comparing the processor peak power limit against a minimum power peak power limit; and
setting the processor peak power limit to the minimum processor peak power limit if the processor peak power limit is less than the minimum power peak power limit.

7. The machine-readable storage media of claim 1 , wherein processor peak power limit is an upper limit of instantaneous peak power that can be provided by a battery and capacitors of a system power rail before the processor is throttled.

8. The machine-readable storage media of claim 1 comprising machine- executable instructions that when executed cause the one or more machines to perform the method comprising:
reading the battery no-load voltage from a fuel gauge of a battery, wherein the battery no- load voltage is a runtime variable.

9. The machine-readable storage media of claim 1 comprising machine- executable instructions that when executed cause one or more machines to perform a method comprising:
lowering the current threshold voltage if it is determined that the processor is not throttling when the processor power limit crosses the peak power of the processor.

10. A system comprising:
a system load comprising a system-on-chip;
a battery having a fuel gauge to provide a battery no-load voltage;
a threshold circuitry to throttle the system-on-chip according to a threshold;
a memory to store a maximum threshold voltage, and a voltage gap between the battery no-load voltage and a previous threshold voltage;
a power manager to:
calculate a current threshold voltage as a function of the battery no-load voltage, the maximum threshold voltage, the voltage gap;
calculate a processor peak power limit as a system peak power limit which in turn is a function of the current threshold voltage;
send the current threshold voltage to the threshold circuitry; and
send the processor peak power limit to the system-on-chip, wherein the current threshold sets a threshold voltage to trigger throttling of the system load to manage peak power of the system load.

11. The system of claim 10 , wherein the power manager is to calculate a system peak power as a function of the current threshold voltage, the battery no-load voltage, a system power rail capacitance, a time between system voltage drops below the current voltage threshold and the system reduces peak power, a battery resistance, and a minimum voltage level of the system power rail.

12. The system of claim 11 , wherein the memory stores the system power rail capacitance, and the time between system voltage drops below the current voltage threshold and the system reduces peak power.

13. The system of claim 11 , wherein the fuel gauge provides the battery resistance.

14. The system of claim 11 , wherein the power manager is to scale a difference between the system peak power and power by rest of platform, wherein the power by rest of platform is part of the system load.

15. The system of claim 14 , wherein the power manager is to account for power conversion loss of a voltage regulator to scale the difference.

16. The system of claim 14 , wherein the power manager is to:
compare the processor peak power limit against a maximum power peak power limit; and
set the processor peak power limit to the maximum processor peak power limit if the processor peak power limit is greater than the maximum power peak power limit.

17. The system of claim 14 , wherein the power manager is to:
compare the processor peak power limit against a minimum power peak power limit; and
set the processor peak power limit to the minimum processor peak power limit if the processor peak power limit is less than the minimum power peak power limit.

18. An apparatus comprising:
a processor; and
a power manager coupled to the processor to dynamically adjust a threshold voltage that determines when to throttle the processor, and to determine a peak power limit for the processor to increase performance of the processor, wherein the power manager is to dynamically adjust the threshold voltage to track a no-load voltage of a battery supplying power to the processor, wherein the power manager is to read the battery no-load voltage and a battery impedance from a battery fuel gauge to determine the threshold voltage.

19. The apparatus of claim 18 , wherein the power manager is to:
compare the peak power limit against a maximum power peak power limit; and
set the peak power limit to the maximum peak power limit if the peak power limit is greater than the maximum power peak power limit.

Assignees

• Intel Corp

Inventors

• Nge Chee Lim
• Uan-Zo-Li Alexander
• Wang Zhongsheng
• Hermerding Ii James
• Magi Caren

Classifications

• G06F1/325

  Power saving in peripheral device · CPC title

• H02J2207/50

  Charging of capacitors, supercapacitors, ultra-capacitors or double layer capacitors · CPC title

• G06F1/26 Primary

  Power supply means, e.g. regulation thereof (for memories G11C) · CPC title

• G01R19/165

  Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values · CPC title

• G06F1/30

  Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations (for resetting only G06F1/24) · CPC title