Peak power determination for an integrated circuit device

Patent metadata

Field	Value
Publication number	US-2020264692-A1
Application number	US-201716642694-A
Country	US
Kind code	A1
Filing date	Sep 28, 2017
Priority date	Sep 28, 2017
Publication date	Aug 20, 2020
Grant date	—

Abstract

Peak power setting circuitry is provided to set a peak power value for an integrated circuit device. A power supply interface is to receive a value to estimate a peak power capacity of a power supply serving the integrated circuit device and processing circuitry is provided to calculate an approximate peak power for the integrated circuit device. A peak power for the integrated circuit device is determined by increasing the approximate peak power depending on an amount by which the integrated circuit device power is reduced in response to assertion of a throttling signal.

First claim

1 - 25 . (canceled)

26 . A circuit comprising peak power setting circuitry to set a peak power value for an integrated circuit device, the integrated circuit device having throttling circuitry to assert a power reducing feature of the integrated circuit device in response to a throttling signal assertion, the peak power setting circuitry including:
a power supply interface to receive a value to estimate a peak power capacity of a power supply serving the integrated circuit device; processing circuitry to: determine an approximate peak power for the integrated circuit device using the estimated peak power capacity of the power supply; and determine a peak power for the integrated circuit device by increasing the approximate peak power for the integrated circuit device depending on an amount by which the integrated circuit device power is reduced in response to assertion of the throttling signal.

27 . The circuit of claim 26 , wherein the value to estimate the peak power capacity of the power supply comprises at least one of a peak battery power, a peak adapter power and a dedicated power supply.

28 . The circuit of claim 26 , wherein the throttling signal assertion indicates that at least one of a threshold voltage, a threshold power and a threshold current has been crossed.

29 . The circuit of claim 28 , wherein the processing circuitry is to determine at least one further peak power for the integrated circuit device, the at least one further peak power having a further approximate peak power different from the approximate peak power and wherein the further peak power has a respective further throttling signal to which the integrated circuit device has a corresponding power-reducing response.

30 . The circuit of claim 29 , wherein the peak power corresponds to a first power limit up to which the integrated circuit is permitted to sustain power for up to a first duration of time whereas the further peak power corresponds to a second power limit up to which the integrated circuit is permitted to sustain power for a second duration of time, wherein the second duration of time is different from the first duration of time.

31 . The circuit of claim 26 , the processing circuitry comprising:
correction circuitry to correct the determined peak power for the integrated circuit depending on a number of assertions of the throttling signal in a given time period.

32 . The circuit of claim 31 , wherein the correction to the determined peak power comprises decreasing the determined peak power relative to the increased approximate peak power when the number of assertions of the throttling signal in the given time period is higher than a threshold maximum number of throttling assertions.

33 . The circuit of claim 31 , wherein the correction to the determined peak power comprises increasing the determined peak power relative to the increased approximate peak power when the number of assertions of the throttling signal in the given time period is lower than a threshold minimum number of throttling assertions.

34 . The circuit of claim 31 , further comprising interrupt generating circuitry to send an interrupt to the processing circuitry responsive to at least one of: the number of throttling signal assertions exceeding the threshold maximum number in the given time period; or the number of throttling signal assertions being less than the threshold minimum number in the given time period.

35 . The circuit of claim 31 , wherein the correction circuitry is to determine the correction iteratively in response to at least one of: updates to the number of assertions of the throttling signal and updates to the estimated peak power capacity of the power supply.

36 . The circuit of claim 35 , wherein the correction circuitry is to implement a Proportional Integral Differential algorithm to perform the iterative correction.

37 . The circuit of claim 26 , wherein the processing circuitry is responsive to an indication from a battery fuel gauge of a change in a peak power capability of a battery or of a battery state of charge, to update the peak power determination using an updated value for the estimated peak power supply capacity.

38 . The circuit of claim 26 , comprising threshold calculation circuitry to calculate the at least one of a threshold voltage, a threshold power and a threshold current depending on the determined peak power for the integrated circuit device.

39 . The circuit of claim 38 , wherein the threshold calculation circuitry is arranged to calculate the at least one of the threshold voltage, threshold power and threshold current using an estimate for an impedance of the battery supply based on a peak battery power.

40 . The circuit of claim 39 , wherein the threshold calculation circuitry is to calculate the peak battery power based on the determined peak power for the integrated circuit device.

41 . The circuit of claim 39 , wherein the threshold calculation circuitry is to calculate the peak battery power based on at least one of: a peak power of an adapter of the power supply and the estimated power consumption of the ROP excluding the integrated circuit device.

42 . The circuit of claim 38 , wherein the threshold calculation circuitry is arranged to calculate the at least one of the threshold voltage, threshold power and threshold current using a duration of time between the throttling signal being asserted and the power reducing feature taking effect to reduce the power.

43 . The circuit of claim 26 , wherein the power supply comprises a battery unit and wherein the power supply interface is to receive a value for a peak power capability of the battery unit and wherein the peak power capacity of the power supply is estimated using the peak power value of the battery unit.

44 . The circuit of claim 26 , wherein the power supply interface is to receive an adapter peak power value and wherein the data processing circuitry is to estimate the peak power capacity of the power supply using the adapter peak power value.

45 . The circuit of claim 26 , further comprising the integrated circuit.

46 . The circuit of claim 26 , wherein peak power setting circuitry is included in an embedded controller.

47 . At least one non-transitory machine-readable medium having instructions stored thereon that, when executed, cause processing hardware to:
receive at least one value to estimate a peak power capacity of a power supply serving an integrated circuit device; determining an approximate peak power for the integrated circuit device based on the estimated peak power capacity of the power supply; and determine a peak power for the integrated circuit device by increasing the approximate peak power for the integrated circuit device according to a peak power enhancement function, wherein the peak power enhancement function depends on an amount by which the integrated circuit device power is reduced by the integrated circuit device in response to assertion of a throttling signal.

48 . The at least one non-transitory machine-readable medium of claim 47 , wherein the instructions, when executed, are further to implement an operating system.

49 . A method of setting a peak power value for an integrated circuit device, the integrated circuit device having power management circuitry to implement a power reducing feature of the integrated circuit device in response to a throttling signal assertion, the method comprising:
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Assignees

• Intel Corp

Inventors

• Gorbatov Eugene
• Uan-Zo-Li Alexander
• Nge Chee Lim
• Hermerding Ii James
• Wang Zhongsheng

Classifications

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F1/28 Primary

  Supervision thereof, e.g. detecting power-supply failure by out of limits supervision · CPC title

• G06F1/3296 Primary

  by lowering the supply or operating voltage · CPC title

• G06F1/30

  Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations (for resetting only G06F1/24) · CPC title