Transition metal dichalcogenide nanowires and methods of fabrication

Patent metadata

Field	Value
Publication number	US-12176388-B2
Application number	US-202016914137-A
Country	US
Kind code	B2
Filing date	Jun 26, 2020
Priority date	Jun 26, 2020
Publication date	Dec 24, 2024
Grant date	Dec 24, 2024

Abstract

A transistor structure includes a first channel layer over a second channel layer, where the first and the second channel layers include a monocrystalline transition metal dichalcogenide (TMD). The transistor structure further includes a source material coupled to a first end of the first and second channel layers, a drain material coupled to a second end of the first and second channel layers, a gate electrode between the source material and the drain material, and between the first channel layer and the second channel layer and a gate dielectric between the gate electrode and each of the first channel layer and the second channel layer.

First claim

What is claimed is:

1. A transistor structure comprising:
a first channel layer vertically over a second channel layer, wherein the first and the second channel layers comprise a monocrystalline transition metal dichalcogenide (TMD);
a source material coupled to a first end of the first and second channel layers;
a drain material coupled to a second end of the first and second channel layers;
a gate electrode laterally between the source material and the drain material, and vertically between the first channel layer and the second channel layer; and
a gate dielectric between the gate electrode and each of the first channel layer and the second channel layer.

2. The transistor structure of claim 1 , wherein the monocrystalline TMD of the first channel layer has a first crystal orientation, and the monocrystalline TMD of the second channel layer has the first crystal orientation.

3. The transistor structure of claim 1 , wherein the each of the first channel layer and the second channel layer comprise a plurality of stacked 2-dimensional TMD layers.

4. The transistor structure of claim 1 , wherein the monocrystalline TMD comprises at least one of molybdenum, tungsten or chromium, and at least one of sulfur, selenium or tellurium.

5. The transistor structure of claim 1 , wherein the first channel layer and the second channel layer each have a thickness between 1 and 4 monolayers.

6. The transistor structure of claim 1 , wherein each of the first and second channel layers have a first thickness along a first direction orthogonal to a longitudinal length, wherein each of the first and second channel layers have a second thickness along a second direction orthogonal to the first direction and to the longitudinal length, wherein the first thickness is between 5 nm and 60 nm, and wherein the second thickness is between 1 and 4 monolayers.

7. The transistor structure of claim 1 , wherein the gate electrode is directly adjacent to a first portion of the gate dielectric on a top surface of the first channel layer and directly adjacent a second portion of the gate dielectric on a bottom surface of the second channel layer.

8. The transistor structure of claim 1 , wherein the source material and the drain material are epitaxial to the monocrystalline TMD.

9. A transistor structure comprising:
a first nanowire above a second nanowire, wherein the first and the second nanowires comprise a crystal of a group III-Nitride (III-N) material;
a first channel layer comprising a monocrystalline transition metal dichalcogenide (TMD) directly adjacent the first nanowire;
a second channel layer comprising the monocrystalline TMD directly adjacent the second nanowire;
a source material coupled to a first end of the first and second channel layers;
a drain material coupled to a second end of the first and second channel layers;
a gate electrode between the source material and the drain material and between the first nanowire and the second nanowire; and
a gate dielectric between the gate electrode and each of the first channel layer and the second channel layer.

10. The transistor structure of claim 9 , wherein the monocrystalline TMD of the first channel layer has a first crystal orientation, and the monocrystalline TMD of the second channel layer has the first crystal orientation, and wherein the monocrystalline TMD of the first channel layer and the monocrystalline TMD of the second channel layer are lattice matched to the crystal of the group III-N material.

11. The transistor structure of claim 9 , wherein the monocrystalline TMD comprises at least one of molybdenum, tungsten or chromium, and at least one of sulfur, selenium or tellurium, and wherein the group III-N material comprises nitrogen and at least one of Al or In.

12. The transistor structure of claim 9 , wherein each of the first nanowire and the second nanowire have a first thickness along a first direction orthogonal to a longitudinal length, wherein each of the first nanowire and the second nanowire have a second thickness along a second direction orthogonal to the first direction and to the longitudinal length, wherein the first thickness is between 5 nm and 60 nm, and wherein the second thickness is between 4 and 8 nm.

13. The transistor structure of claim 9 , wherein the first channel layer is on a top surface and on a bottom surface of the first nanowire and the second channel layer is on a top surface and on a bottom surface of the second nanowire.

14. The transistor structure of claim 13 , wherein the gate electrode is above the top surface of the first nanowire and below the bottom surface of the second nanowire and the gate dielectric is between the gate electrode and the first channel layer above the top surface of the first nanowire and between the gate electrode and the second channel layer below the bottom surface of the second nanowire.

15. The transistor structure of claim 13 , wherein each of the first channel layer and the second channel layer each have a thickness between 1 and 4 monolayers.

16. The transistor structure of claim 13 , wherein the first channel layer is on a sidewall surface of the first nanowire and the second channel layer is on a sidewall surface of the second nanowire.

17. A transistor structure comprising:
a first channel layer over a second channel layer, wherein the first and the second channel layers comprise a monocrystalline transition metal dichalcogenide (TMD);
a source material coupled to a first end of the first and second channel layers;
a drain material coupled to a second end of the first and second channel layers, wherein the source material and the drain material are epitaxial to the monocrystalline TMD;
a gate electrode between the source material and the drain material, and between the first channel layer and the second channel layer; and
a gate dielectric between the gate electrode and each of the first channel layer and the second channel layer.

18. The transistor structure of claim 17 , wherein the monocrystalline TMD of the first channel layer has a first crystal orientation, and the monocrystalline TMD of the second channel layer has the first crystal orientation.

19. The transistor structure of claim 17 , wherein the each of the first channel layer and the second channel layer comprise a plurality of stacked 2-dimensional TMD layers.

20. The transistor structure of claim 17 , wherein the monocrystalline TMD comprises at least one of molybdenum, tungsten or chromium, and at least one of sulfur, selenium or tellurium.

Assignees

• Intel Corp

Inventors

• O'Brien Kevin
• Dorow Chelsey
• Maxey Kirby
• Naylor Carl
• Shivaraman Shriram
• Lee Sudarat
• Gosavi Tanay
• Lin Chia-Ching
• Avci Uygar
• Penumatcha Ashish Verma

Classifications

• H10P14/2926

  Crystal orientations · CPC title

• H10P14/3416

  Nitrides · CPC title

• H10P14/3216

  Nitrides · CPC title

• H10P14/3252

  Alternating layers, e.g. superlattice · CPC title

• H10P14/3236

  being chalcogenide semiconducting materials not being oxides, e.g. ternary compounds · CPC title