Microelectronic component having molded regions with through-mold vias

Patent metadata

Field	Value
Publication number	US-12176292-B2
Application number	US-202318375867-A
Country	US
Kind code	B2
Filing date	Oct 2, 2023
Priority date	Mar 25, 2020
Publication date	Dec 24, 2024
Grant date	Dec 24, 2024

Abstract

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic component may include a substrate having a first face and an opposing second face, wherein the substrate includes a through-substrate via (TSV); a first mold material region at the first face, wherein the first mold material region includes a first through-mold via (TMV) conductively coupled to the TSV; and a second mold material region at the second face, wherein the second mold material region includes a second TMV conductively coupled to the TSV.

First claim

The invention claimed is:

1. A microelectronic assembly, comprising:
a package substrate having a first side and a second side, the second side opposite the first side;
a microelectronic component having a first side and a second side, the second side opposite the first side, and the microelectronic component having a first sidewall and a second sidewall between the first side and the second side, the first sidewall laterally opposite the second sidewall, wherein a first plurality of interconnects is between the second side of the microelectronic component and the first side of the package substrate;
a first insulating layer having a first portion laterally adjacent to the first sidewall of the microelectronic component, and the first insulating layer having a second portion laterally adjacent to the second sidewall of the microelectronic component;
a first plurality of through vias in the first portion of the first insulating layer, the first plurality of through vias laterally spaced apart from the first sidewall of the microelectronic component, and the first plurality of through vias coupled to the first side of the package substrate by a second plurality of interconnects;
a second plurality of through vias in the second portion of the first insulating layer, the second plurality of through vias laterally spaced apart from the second sidewall of the microelectronic component, and the second plurality of through vias coupled to the first side of the package substrate by a third plurality of interconnects;
a first underfill layer between the first insulating layer and the package substrate and between the microelectronic component and the package substrate, the first underfill layer around the first plurality of interconnects, the first underfill layer around the second plurality of interconnects, and the first underfill layer around the third plurality of interconnects;
a first die over a first portion of the microelectronic component and over the first plurality of through vias, the first die coupled to the first side of the microelectronic component and to the first plurality of through vias by a fourth plurality of interconnects;
a second die over a second portion of the microelectronic component and over the second plurality of through vias, the second die coupled to the first side of the microelectronic component and to the second plurality of through vias by a fifth plurality of interconnects;
a second underfill layer between the first portion of the first insulating layer and the first die and between the second portion of first insulating layer and the second die, the second underfill layer around the fourth plurality of interconnects, and the second underfill layer around the fifth plurality of interconnects;
a second insulating layer having a first portion laterally adjacent to and in contact with a side of the first die; and
a sixth plurality of interconnects beneath the second side of the package substrate, the sixth plurality of interconnects vertically beneath the second side of the microelectronic component, vertically beneath the first plurality of through vias, and vertically beneath the second plurality of through vias.

2. The microelectronic assembly of claim 1 , wherein the second side of the microelectronic component is coupled to the first side of the package substrate by the first plurality of interconnects.

3. The microelectronic assembly of claim 1 , wherein the second insulating layer has a second portion laterally adjacent to and in contact with a side of the second die.

4. The microelectronic assembly of claim 1 , wherein the second insulating layer is in contact with the second underfill layer.

5. The microelectronic assembly of claim 1 , wherein the second insulating layer is over the first die and over the second die.

6. The microelectronic assembly of claim 1 , wherein the microelectronic component has a substrate comprising silicon.

7. The microelectronic assembly of claim 6 , wherein the microelectronic component comprises a plurality of through silicon vias.

8. The microelectronic assembly of claim 1 , wherein the microelectronic component has an insulating substrate.

9. A microelectronic assembly, comprising:
a package substrate having a first side and a second side, the second side opposite the first side;
a bridge having a substrate comprising silicon, the bridge having a first side and a second side, the second side opposite the first side, and the bridge having a first sidewall and a second sidewall between the first side and the second side, the first sidewall laterally opposite the second sidewall, wherein a first plurality of interconnects is between the second side of the bridge and the first side of the package substrate;
a first mold layer having a first portion laterally adjacent to the first sidewall of the bridge, and the first mold layer having a second portion laterally adjacent to the second sidewall of the bridge;
a first plurality of through vias in the first portion of the first mold layer, the first plurality of through vias laterally spaced apart from the first sidewall of the bridge, and the first plurality of through vias coupled to the first side of the package substrate by a second plurality of interconnects;
a second plurality of through vias in the second portion of the first mold layer, the second plurality of through vias laterally spaced apart from the second sidewall of the bridge, and the second plurality of through vias coupled to the first side of the package substrate by a third plurality of interconnects;
a first underfill layer between the first mold layer and the package substrate and between the bridge and the package substrate, the first underfill layer around the first plurality of interconnects, the first underfill layer around the second plurality of interconnects, and the first underfill layer around the third plurality of interconnects;
a first die over a first portion of the bridge and over the first plurality of through vias, the first die coupled to the first side of the bridge and to the first plurality of through vias by a fourth plurality of interconnects;
a second die over a second portion of the bridge and over the second plurality of through vias, the second die coupled to the first side of the bridge and to the second plurality of through vias by a fifth plurality of interconnects;
a second underfill layer between the first portion of the first mold layer and the first die and between the second portion of first mold layer and the second die, the second underfill layer around the fourth plurality of interconnects, and the second underfill layer around the fifth plurality of interconnects;
a second mold layer having a first portion laterally adjacent to and in contact with a side of the first die; and
a sixth plurality of interconnects beneath the second side of the package substrate, the sixth plurality of interconnects vertically beneath the second side of the bridge, vertically beneath the first plurality of through vias, and vertically beneath the second plurality of through vias.

10. The microelectronic assembly of claim 9 , wherein the second side of the bridge is coupled to the first side of the package substrate by the first plurality of interconnects.

11. The microelectronic assembly of claim 9 , wherein the second mold layer has a second portion laterally adjacent to and in contact with a side of the second die, and wherein the second mold layer is in contact with the second underfill layer.

12. The microelectronic assembly of claim 9 , wherein the bridge comprises a plurality of through silicon vias.

13. A method of fabricating a microelectro

Assignees

• Intel Corp

Inventors

• Ganesan Sanka
• Viswanath Ram
• Brun Xavier Francois
• Ibrahim Tarek A
• Gamba Jason M
• Dubey Manish
• May Robert Alan

Classifications

• H10W70/618

  the bridge chips being embedded in the package substrates, interposers or redistribution layers · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title

• H10W90/722

  between stacked chips · CPC title