Semiconductor package with wettable flank

Patent metadata

Field	Value
Publication number	US-12176272-B2
Application number	US-202218056304-A
Country	US
Kind code	B2
Filing date	Nov 17, 2022
Priority date	Dec 29, 2020
Publication date	Dec 24, 2024
Grant date	Dec 24, 2024

Abstract

Implementations of the semiconductor package may include a first sidewall opposite a second sidewall, and a third sidewall opposite a fourth sidewall. Implementations of the semiconductor package may include a first lead and a second lead extending from the first sidewall and a first half-etched tie bar directly coupled to the first lead. An end of the first half-etched tie bar may be exposed on the third sidewall of the semiconductor package. Implementations of the semiconductor package may also include a second half-etched tie bar directly coupled to the second lead. An end of the second half-etched tie bar may be exposed on the fourth sidewall. An end of the first lead and an end of the second lead may each be electroplated. The first die flag and the second die flag may be electrically isolated from the first lead and the second lead.

First claim

What is claimed is:

1. A semiconductor package comprising:
a first surface opposite a second surface;
a first sidewall opposite a second sidewall, the first sidewall and second sidewall coupled between the first surface and the second surface;
a third sidewall opposite a fourth sidewall, the third sidewall and fourth sidewall coupled between the first surface and the second surface;
a first lead extending from the first sidewall;
a first half-etched tie bar directly coupled to the first lead, wherein an end of the first half-etched tie bar is exposed on the third sidewall; and
a mold compound at least partially encapsulating the first lead and the first half-etched tie bar;
wherein an end of the first lead is electroplated.

2. The semiconductor package of claim 1 , wherein the mold compound is between the first surface and the first half-etched tie bar.

3. The semiconductor package of claim 1 , further comprising a second lead and a third lead extending from the first sidewall.

4. The semiconductor package of claim 3 , further comprising a second half-etched tie bar directly coupled to the second lead and a third half-etched tie bar directly coupled to the third lead, wherein an end of the second half-etched tie bar is exposed on the third side of the semiconductor package and an end of the third half-etched tie bar is exposed on the fourth side of the semiconductor package.

5. The semiconductor package of claim 3 , further comprising a trench extending into the first surface, wherein the trench separates the first lead, the second lead, and the third lead from a die flag.

6. The semiconductor package of claim 5 , wherein an end of a second half-etched tie bar and an end of a third half-etched tie bar are exposed on a sidewall of the trench.

7. The semiconductor package of claim 1 , wherein the first half-etched tie bar is used to electroplate the first lead.

8. The semiconductor package of claim 1 , wherein the end of the first lead extends from the first sidewall at least 8 micrometers.

9. A semiconductor package comprising:
a first surface opposite a second surface;
a first sidewall opposite a second sidewall, the first sidewall and second sidewall coupled between the first surface and the second surface;
a third sidewall opposite a fourth sidewall, the third sidewall and fourth sidewall coupled between the first surface and the second surface;
a first lead extending from the first sidewall;
a first half-etched tie bar directly coupled to the first lead, wherein an end of the first half-etched tie bar is exposed on the third sidewall;
a die flag; and
a mold compound at least partially encapsulating the first lead, the first half-etched tie bar, and the die flag;
wherein the die flag is electrically isolated from the first lead.

10. The semiconductor package of claim 9 , wherein the mold compound is between the first surface and the first half-etched tie bar.

11. The semiconductor package of claim 9 , further comprising a second lead and a third lead extending from the first sidewall.

12. The semiconductor package of claim 11 , further comprising a second half-etched tie bar directly coupled to the second lead and a third half-etched tie bar directly coupled to the third lead, wherein an end of the second half-etched tie bar is exposed on the third side of the semiconductor package and an end of the third half-etched tie bar is exposed on the fourth side of the semiconductor package.

13. The semiconductor package of claim 11 , further comprising a trench extending into the first surface, wherein the trench separates the first lead, the second lead, and the third lead from a die flag.

14. The semiconductor package of claim 13 , wherein an end of a second half-etched tie bar and an end of a third half-etched tie bar are exposed on a sidewall of the trench.

15. A semiconductor package comprising:
a first surface opposite a second surface;
a first sidewall opposite a second sidewall, the first sidewall and second sidewall coupled between the first surface and the second surface;
a third sidewall opposite a fourth sidewall, the third sidewall and fourth sidewall coupled between the first surface and the second surface;
a first lead and a second lead extending from the first sidewall;
a first half-etched tie bar directly coupled to the first lead, wherein an end of the first half-etched tie bar is exposed on the third sidewall;
one or more die flags; and
a mold compound at least partially encapsulating the first lead, the first half-etched tie bar, and the one or more die flags;
wherein the one or more die flags are electrically isolated from the first lead and the second lead.

16. The semiconductor package of claim 15 , wherein the mold compound is between the first surface and the first half-etched tie bar.

17. The semiconductor package of claim 15 , further comprising a second lead and a third lead extending from the first sidewall.

18. The semiconductor package of claim 17 , further comprising a second half-etched tie bar directly coupled to the second lead and a third half-etched tie bar directly coupled to the third lead, wherein an end of the second half-etched tie bar is exposed on the third side of the semiconductor package and an end of the third half-etched tie bar is exposed on the fourth side of the semiconductor package.

19. The semiconductor package of claim 15 , wherein the first half-etched tie bar is used to electroplate the first lead.

20. The semiconductor package of claim 15 , wherein the end of the first lead extends from the first sidewall at least 8 micrometers.

Assignees

• Semiconductor Components Ind Llc

Inventors

• Ler Hui Min
• Wang Soon Wei
• Chew Chee Hiong

Classifications

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W90/811

  Multiple chips on leadframes · CPC title

• H10W74/111

  the semiconductor body being completely enclosed · CPC title

• H10W74/016

  using moulds · CPC title

• H10W70/466

  Tape carriers or flat leads · CPC title