System on chip and application processor

Patent metadata

Field	Value
Publication number	US-12174683-B2
Application number	US-202217956195-A
Country	US
Kind code	B2
Filing date	Sep 29, 2022
Priority date	Oct 1, 2021
Publication date	Dec 24, 2024
Grant date	Dec 24, 2024

Abstract

A system on chip (SoC) and an application processor are provided. The SoC includes a memory controller configured to control a memory; a plurality of function modules configured to access the memory through a memory interface; a system interconnect circuit configured to operate based on a first clock signal and connect the memory interface and the plurality of function modules; and a power controller configured to control the first clock signal to be periodically gated, and control the memory to operate in a lower-power mode during a period in which the first clock signal is gated.

First claim

What is claimed is:

1. A system on chip (SoC) comprising:
a memory controller configured to control a memory;
a plurality of circuitries configured to operate based on a plurality of internal clock signals, respectively, and to transmit a plurality of activity request signals, respectively to request access to the memory through a memory interface;
a system interconnect circuit configured to selectively connect the memory interface and the plurality of circuitries based on a first clock signal by,
allowing one or more of the plurality of circuitries to access the memory in an ungating period in which the first clock signal is ungated, and
inhibiting all of the plurality of circuitries from accessing the memory by simultaneously blocking generation of each of the plurality of internal clock signals in a gating period in which the first clock signal is gated; and

a power controller configured to control the first clock signal to be periodically gated in response to an active level of one or more of the plurality of activity request signals being a default setting, and control the memory to operate in a lower-power mode during a period in which the first clock signal is gated.

2. The SoC of claim 1 , wherein the power controller is further configured to control the first clock signal to be gated and ungated in a first cycle, and wherein the gating period of the first clock signal is longer than the ungating period of the first clock signal.

3. The SoC of claim 1 , wherein the power controller is further configured to control the first clock signal to be ungated in response to the active level of a first activity request signal among the plurality of activity request signals received from the plurality of circuitries.

4. The SoC of claim 3 , wherein
a first circuitry among the plurality of circuitries is configured to transmit the first activity request signal having the active level to the power controller, and
the first circuitry is a circuitry with access to the memory in real time or has a highest performance among the plurality of circuitries.

5. The SoC of claim 3 , wherein one of the plurality of circuitries comprises a data queue among the plurality of circuitries and is configured to transmit the first activity request signal having the active level to the power controller when the data queue is in a full state or an empty state.

6. The SoC of claim 1 , wherein the power controller is further configured to control the first clock signal to be gated in response to the plurality of activity request signals received from the plurality of circuitries having respective inactive levels.

7. The SoC of claim 1 , wherein the power controller is further configured to transmit a clock gating control signal controlling gating and ungating of the first clock signal to a first clock management circuit included in the system interconnect circuit, and transmit a power mode control signal controlling a power mode of the memory to the memory controller.

8. The SoC of claim 7 , wherein the first clock management circuit is further configured to generate a plurality of clock signals used in the system interconnect circuit based on the first clock signal, and block generation of the plurality of clock signals by gating the first clock signal, in response to a first level of the clock gating control signal indicating gating enable.

9. The SoC of claim 7 , further comprising:
a sub-interconnect circuit configured to operate based on a second clock signal to connect at least two of the plurality of circuitries to the system interconnect circuit, and control gating of the second clock signal based on the clock gating control signal received from the power controller.

10. The SoC of claim 9 , wherein the sub-interconnect circuit comprises a second clock management circuit configured to generate a plurality of clock signals used in the sub-interconnect circuit based on the second clock signal; and
a sub-controller configured to
receive the clock gating control signal from the power controller, control gating of the second clock signal based on the clock gating control signal,
generate an activity request signal based on at least one activity signal of a high importance among at least two active signals received from the at least two of the plurality of circuitries, and
transmit the activity request signal to the power controller.

11. The SoC of claim 7 , wherein at least one of the plurality of circuitries comprises a third clock management circuit configured to generate a plurality of clock signals used in the at least one of the plurality of circuitries based on a third clock signal, and gate the third clock signal based on the clock gating control signal received from the power controller.

12. The SoC of claim 1 , wherein the memory comprises a dynamic random access memory (DRAM).

13. The SoC of claim 1 , wherein the power controller is further configured to periodically gate the first clock signal in the lower-power mode of a system and adjust a dynamic voltage and frequency scaling (DVFS) level with respect to the plurality of circuitries and the system interconnect circuit in a normal mode of the system.

14. A system on chip (SoC) comprising:
a plurality of circuitries configured to operate based on a plurality of internal clock signals, respectively, and to transmit a plurality of activity request signals, respectively to request access to a memory, the plurality of circuitries including first circuitry configured to transmit a first activity request signal and a plurality of second circuitry configured to transmit a second activity request signal;
a system interconnect circuit configured to selectively provide a data transmission path between the plurality of circuitries and the memory based on a first clock signal by,
allowing one or more of the plurality of second circuitry to access the memory in an ungating period in which the first clock signal is ungated, and
inhibiting all of the plurality of second circuitry from accessing the memory by simultaneously blocking generation of each of the plurality of internal clock signals in a gating period in which the first clock signal is gated; and

a power controller configured to,
receive an activity request signal from each of the plurality of circuitries,
control gating and ungating of the first clock signal of the system interconnect circuit based on the plurality of activity request signals received from the plurality of circuitries by ungating the first clock signal in response to an active level of the first activity request signal received from the first circuitry, and periodically gating the first clock signal in response to the active level of the second activity request signal received from the plurality of second circuitry, and
control the memory to operate in a lower-power mode during a period in which the first clock signal is gated.

15. The SoC of claim 14 , wherein the active level of at least one first activity request signal is of a high importance among the plurality of activity request signals, and the second activity request signal is of a low importance among the plurality of activity request signals.

16. The SoC of claim 14 , wherein the power controller is further configured to control the first clock signal to be gated in response to all of the plurality of activity request signals having respective inactive levels.

17. The SoC of claim 14 , wherein
the memory is configured to operate in a normal power mode in a first period in which the first clock signal is gated, and in the lower-power mode in a s

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yoo Junhee
• Kim Jaehyun
• Ahn Jingyu
• Kim Wooil
• Jo Manhwee

Classifications

• G11C7/222

  Clock generating, synchronizing or distributing circuits within memory device · CPC title

• G06F1/3243

  Power saving in microcontroller unit · CPC title

• G06F1/3296

  by lowering the supply or operating voltage · CPC title

• G06F1/324 Primary

  by lowering clock frequency · CPC title

• G06F15/7896

  Modular architectures, e.g. assembled from a number of identical packages · CPC title