Memory time-sharing method and apparatus capable of distributing bus traffic of system-on-chip

Patent metadata

Field	Value
Publication number	US-10649929-B2
Application number	US-201715645299-A
Country	US
Kind code	B2
Filing date	Jul 10, 2017
Priority date	Jul 10, 2017
Publication date	May 12, 2020
Grant date	May 12, 2020

Abstract

A bus system is proposed, which includes M (M is a natural number) master ports, N (N is a natural number) slave ports, a bus, A (A is a natural number) masters, B (B is a natural number) salves, and an internal memory. The bus system includes P (P is a natural number, P≤M) master ports, a traffic monitoring unit, Q (Q is a natural number, Q≤N) slaves, a port traffic monitoring unit, and a memory clock scaling unit. Accordingly, in a system-on-chip using a low-power processor, a memory clock of an internal memory connected to a plurality of slave ports is scaled so as to distribute bus traffic.

First claim

What is claimed is:

1. A bus system comprising:
a bus with M master ports and N slave ports connected thereto, where M is a natural number and N is a natural number;
A masters connected to the M master ports, respectively, where A is a natural number;
B slaves connected to the N slave ports, respectively, where B is a natural number;
an internal memory controller connected to C slave ports that are selected according to predetermined priority among the N slave ports, where C is a natural number and C≤N; and
a memory clock scaling unit connected to an internal memory comprising the internal memory controller and configured to scale a memory clock of the internal memory based on the number of slave ports connected to the internal memory controller,
wherein the A masters command the B slaves to perform a predetermined operation, the B slaves perform an operation according to commands issued by the A masters, the bus transmits each of the commands issued by the A masters to the B slaves based on a bus clock, and the internal memory writes data based on a memory clock,
wherein the memory clock of the internal memory is scaled to S times the bus clock by the memory clock scaling unit, where S is a natural number.

2. The bus system of claim 1 , wherein the bus is configured in such a way that the M master ports as a horizontal axis and the N slave ports as a vertical axis are connected in a matrix form.

3. The bus system of claim 1 , further comprising a port traffic monitoring unit connected to P mater ports that are selected according to predetermined priority among the M master ports, connected Q slave ports that are selected according to predetermined priority among the N slave ports, and configured to monitor at least one port among the M master ports and the Q slave ports, where P is a natural number, P≤M, Q is a natural number, and Q≤N.

4. The bus system of claim 3 , wherein the port traffic monitoring unit monitors traffic of at least port among the P master ports and the Q slave ports using at least one of a weighting and number of command signals.

5. The bus system of claim 1 , further comprising a port traffic monitoring unit connected to P mater ports that are selected according to predetermined priority among the M master ports, connected Q slave ports that are selected according to predetermined priority among the N slave ports, and configured to monitor at least one port among the M master ports and the Q slave ports, where P is a natural number, P≤M, Q is a natural number, and Q≤N
wherein the memory clock scaling unit scales the memory clock using traffic of a port monitored by the port traffic monitoring unit.

6. The bus system of claim 1 , wherein the bus is based on an advanced high performance bus (AHB) interface.

7. The bus system of claim 1 , wherein the internal memory is a static random access memory (SRAM).

8. A memory time-sharing apparatus comprising:
a bus with M master ports and N slave ports connected thereto where M is a natural number and N is a natural number;
A masters connected to the M master ports, respectively, where A is a natural number;
B slaves connected to the N slave ports, respectively, where B is a natural number;
an internal memory controller connected to C slave ports that are selected according to predetermined priority among the N slave ports, where C is a natural number, and C≤N;
a multiplexer connected to the internal memory controller;
a memory unit connected to the multiplexer and configured to write data; and
a memory clock scaling unit connected to an internal memory comprising the internal memory controller and configured to scale a memory clock of the internal memory based on the number of slave ports connected to the internal memory controller,
wherein the A masters command the B slaves to perform a predetermined operation, the B slaves perform an operation according to commands issued by the A masters, the bus transmits each of the commands issued by the A masters to the B slaves based on a bus clock, the internal memory controller controls the commands issued by the A masters according to an order based on the memory clock, and the multiplexer selects one slave port according to predetermined priority among C slave ports connected to the internal memory controller using a multiplexer selection signal, the multiplexer selection signal being operated based on a selection signal clock,
wherein the memory clock of the internal memory is scaled to S times the bus clock by the memory clock scaling unit, where S is a natural number.

9. The memory time-sharing apparatus of claim 8 , wherein the internal memory controller comprises C separate address areas and the C address areas and the C slave ports are connected, respectively.

10. The memory time-sharing apparatus of claim 8 , wherein the number of slave ports connected to the internal memory controller is 2.

11. The memory time-sharing apparatus of claim 10 , wherein the selection signal clock is the same as the bus clock and the memory clock is twice the bus clock.

12. The memory time-sharing apparatus of claim 8 , wherein the number of salve ports connected to the internal memory controller is 4.

13. The memory time-sharing apparatus of claim 12 , wherein the selection signal clock is twice the bus clock and the memory clock is four times the bus clock.

14. A memory time-sharing apparatus comprising:
a bus with M master ports and N slave ports connected thereto where M is a natural number and N is a natural number;
A masters connected to the M master ports, respectively, where A is a natural number;
B slaves connected to the N slave ports, respectively, where B is a natural number;
an internal memory controller connected to C slave ports that are selected according to predetermined priority among the N slave ports, where C is a natural number and C≤N;
C multiplexers connected to the internal memory controller and D slave ports for time-sharing among the N slave ports, where D is a natural number and C+D≤N;
C memory units connected to the C multiplexers, respectively and to configured to write data; and
a memory clock scaling unit connected to an internal memory comprising the internal memory controller and configured to scale a memory clock of the internal memory based on the number of slave ports connected to the internal memory controller,
wherein the A masters command the B slaves to perform a predetermined operation, the B slaves perform an operation according to commands issued by the A masters, the bus transmits each of the commands issued by the A masters to the B slaves based on a bus clock, the internal memory controller controls the commands issued by the A masters according to an order based on the memory clock, and the C multiplexers select one slave port according to predetermined priority among the C slave ports connected to the internal memory controllers using each multiplexer selection signal, the multiplexer selection signal being operated based on a selection signal clock,
wherein the memory clock of the internal memory is scaled to S times the bus clock by the memory clock scaling unit, where S is a natural number.

15. The memory time-sharing apparatus of claim 14 , wherein the internal memory controller comprises a plurality of separate address areas, the plurality of address areas have address areas pointing the A masters, and each of the address areas pointing the A maters has an address area pointing the C slaves.

16. The memory time-sharing apparatus of claim 14 , wherein:
the internal memory controller comprises C separate address areas; and
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Assignees

• Fci Inc
• Dialog Semiconductar Korea Inc

Inventors

• Hwang Chang-Ik

Classifications

• G06F1/10

  Distribution of clock signals {, e.g. skew} · CPC title

• G06F13/1689 Primary

  Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234) · CPC title

• G06F12/063

  for I/O modules, e.g. memory mapped I/O (I/O protocol G06F13/42) · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title