Electronic substrate stacking

Patent metadata

Field	Value
Publication number	US-12170252-B2
Application number	US-202117449280-A
Country	US
Kind code	B2
Filing date	Sep 29, 2021
Priority date	Sep 29, 2021
Publication date	Dec 17, 2024
Grant date	Dec 17, 2024

Abstract

A base substrate, high-k substrate layers on the base substrate with discrete decoupling capacitors embedded, high density substrate layers on the high-k substrate layers supporting wiring and wiring spacing of less than 2 up to about 10 micron width, pitch connectivity between the upper surface of the base substrate and a lower surface of the set of high density substrate layers supports less than 50 up to about 300 micron pitch, the pitch connectivity on an upper surface of the set of high density substrate layers supports less than about 150 micron pitch. A method including attaching a set of metal posts at each contact on a lower surface of a set of high density substrate layers, attaching to a handler, attaching an interconnect layer to a base substrate, and attaching the set of high density substrate layers to the base substrate while aligning each metal post with a contact.

First claim

What is claimed is:

1. A composite substrate comprising:
a base substrate comprising electrical connections on a lower surface, electrical connections on an upper surface, one or more wiring layers electrically connected between the lower surface and the upper surface;
a set of high-k substrate layers electrically and mechanically connected to the upper surface of the base substrate, wherein each layer of the set of high-k substrate layers comprises wiring and vias which connect above and below each layer of the set of high-k substrate layers, wherein a set of one or more discrete decoupling capacitors are embedded into the set of high-k substrate layers; and
a set of high density substrate layers electrically and mechanically connected to an upper surface of the set of high-k substrate layers, wherein each layer of the set of high density substrate layers comprises wiring and vias which connect above and below each layer of the set of high density substrate layers.

2. The composite substrate according to claim 1 , wherein
the base substrate comprises multiple ceramic layers, and
the base substrate comprises power supply lines to the set of high density substrate layers.

3. The composite substrate according to claim 1 , wherein
the base substrate comprises one or more glass layers, and comprises one or more organic dielectric layers, and
the base substrate comprises power supply lines available to the set of high density substrate layers.

4. The composite substrate according to claim 1 , further comprising:
an interconnect layer between the set of high density substrate layers and the base substrate which provides electrical connection between each upper contact of an upper surface of the composite substrate and each lower contact of a lower surface of the set of high density substrate layers.

5. The composite substrate according to claim 1 , further comprising:
one or more layers with embedded discrete components within the set of high density substrate layers.

6. The composite substrate according to claim 1 , further comprising:
one or more layers of the set of high density substrate layers comprises power supply lines of wiring and vias.

7. The composite substrate according to claim 1 , further comprising:
the set of high density substrate layers comprising test contacts and structures.

8. The composite substrate according to claim 1 , wherein
each layer of the set of high density substrate layers comprises wiring of two or more dimensions and vias of two or more dimensions.

9. A composite substrate comprising:
a base substrate comprising a coefficient of thermal expansion (CTE) between 3 and 12 ppm/° Celsius, a surface area greater than 25 mm×25 mm, electrical connections on a lower surface, electrical connections on an upper surface, one or more wiring layers electrically connected between the lower surface and the upper surface;
a set of high-k substrate layers electrically and mechanically connected to the upper surface of the base substrate, wherein each layer of the set of high-k substrate layers comprises wiring and vias which connect above and below each layer of the set of high-k substrate layers, wherein a set of one or more discrete decoupling capacitors are embedded into the set of high-k substrate layers; and
a set of high density substrate layers electrically and mechanically connected to an upper surface of the set of high-k substrate layers, wherein each layer of the set of high density substrate layers comprises wiring and vias which connect above and below each layer of the set of high density substrate layers, wherein each layer of the set of high density substrate layers supports wiring of less than 2 micron up to about 10 micron width, and less than 2 micron to about 10 micron space between wires, wherein a pitch connectivity between the upper surface of the set of high-k substrate layers and a lower surface of the set of high density substrate layers supports less than 50 micron up to about 300 micron pitch, wherein the pitch connectivity on an upper surface of the set of high density substrate layers supports less than about 150 micron pitch.

10. The composite substrate according to claim 9 , wherein
the base substrate comprises multiple ceramic layers, and
the base substrate comprises power supply lines to the set of high density substrate layers.

11. The composite substrate according to claim 9 , wherein
the base substrate comprises one or more glass layers, and comprises one or more organic dielectric layers, and
the base substrate comprises power supply lines available to the set of high density substrate layers.

12. The composite substrate according to claim 9 , wherein
an interconnect layer between the set of high density substrate layers and the base substrate which provides electrical connection between each upper contact of an upper surface of the composite substrate and each lower contact of a lower surface of the set of high density substrate layers.

13. The composite substrate according to claim 9 , wherein
one or more layers with embedded discrete components within the set of high density substrate layers.

14. The composite substrate according to claim 9 , further comprising:
one or more layers of the set of high density substrate layers comprises power supply lines of wiring and vias,
the set of high density substrate layers comprising test contacts and structures, and
each layer of the set of high density substrate layers comprises wiring of two or more dimensions and vias of two or more dimensions.

Assignees

• IBM

Inventors

• Shan Lei
• Friedman Daniel Joseph
• Bonilla Griselda
• Knickerbocker John

Classifications

• H10W70/686

  the multiple insulating layers having different compositions, e.g. polymer layer on glass substrate · CPC title

• H10W70/692

  Ceramics or glasses · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W70/05

  of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) · CPC title

• H10W90/401

  characterised by multiple insulating or insulated package substrates, interposers or RDLs · CPC title