Pixel circuit and driving method therefor, and display panel

US12170064B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12170064-B2
Application numberUS-202318345369-A
CountryUS
Kind codeB2
Filing dateJun 30, 2023
Priority dateJun 30, 2021
Publication dateDec 17, 2024
Grant dateDec 17, 2024

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A pixel circuit, a driving method for a pixel circuit, and a display panel. The pixel circuit includes a drive module, a data write module, a first compensation module, a second compensation module, a light-emitting module, a storage module and a coupling module. The data write module is configured to write a voltage related to a data voltage to a control terminal of the drive module. The drive module is configured to provide a drive signal to the light-emitting module according to the voltage of the control terminal to drive the light-emitting module to emit light. A first terminal of the second compensation module is connected to the control terminal of the drive module, a second terminal of the second compensation module is connected to a first terminal of the first compensation module.

First claim

Opening claim text (preview).

What is claimed is: 1. A pixel circuit comprising: a drive module; a data write module, wherein the data write module is configured to, in a data write and threshold compensation stage, write a voltage related to a data voltage to a control terminal of the drive module; a first compensation module, wherein a second terminal of the first compensation module is connected to a first terminal of the drive module and the first compensation module is configured to, in the data write and threshold compensation stage, perform a threshold compensation on the drive module; a second compensation module, wherein a first terminal of the second compensation module is connected to the control terminal of the drive module and a second terminal of the second compensation module is connected to a first terminal of the first compensation module; a light-emitting module, a storage module, wherein the storage module is configured to store the voltage of the control terminal of the drive module; and a coupling module, wherein the coupling module is configured to, in a compensation adjustment stage, couple a jump voltage or a fixed voltage to at least one of the second terminal of the second compensation module or an internal node of the second compensation module and the drive module is configured to provide a drive signal to the light-emitting module according to the voltage of the control terminal to drive the light-emitting module to emit light. 2. The pixel circuit of claim 1 , wherein the jump voltage is a pulse voltage, the first compensation module comprises a first transistor, the second compensation module comprises a second transistor, the storage module comprises a first capacitor, the coupling module comprises a second capacitor, a gate of the first transistor is connected to a first scan line, a first electrode of the first transistor is connected to the first terminal of the drive module, a second electrode of the first transistor is connected to a second electrode of the second transistor, a first electrode of the second transistor is connected to the control terminal of the drive module, a gate of the second transistor is connected to a second scan line, a first electrode of the first capacitor is connected to the fixed voltage, a second electrode of the first capacitor is connected to the control terminal of the drive module, a first electrode of the second capacitor is configured to receive the pulse voltage, and a second electrode of the second capacitor is connected to the second electrode of the second transistor. 3. The pixel circuit of claim 1 , wherein the jump voltage is a pulse voltage, the first compensation module comprises a first transistor, the second compensation module comprises a second transistor, the storage module comprises a first capacitor, and the coupling module comprises a second capacitor; and wherein a gate of the first transistor is connected to a second scan line, a first electrode of the first transistor is connected to the first terminal of the drive module, a second electrode of the first transistor is connected to a second electrode of the second transistor, a first electrode of the second transistor is connected to the control terminal of the drive module, a gate of the second transistor is connected to the second scan line, a first electrode of the first capacitor is connected to the fixed voltage, a second electrode of the first capacitor is connected to the control terminal of the drive module, a first electrode of the second capacitor is configured to receive the pulse voltage, and a second electrode of the second capacitor is connected to the second electrode of the second transistor. 4. The pixel circuit of claim 3 , wherein the first compensation module comprises the first transistor, the second compensation module comprises the second transistor, the first transistor comprises a double-gate transistor, and the first transistor comprises a first sub-transistor and a second sub-transistor; and wherein a gate of the first sub-transistor and a gate of the second sub-transistor are short-circuited, and the gate of the first sub-transistor and the gate of the second sub-transistor are connected to a same scan line. 5. The pixel circuit of claim 1 , wherein the first compensation module comprises a first transistor, the second compensation module comprises a second transistor, the second transistor comprises a double-gate transistor, the second transistor comprises a first sub-transistor and a second sub-transistor, a first electrode of the first transistor is connected to the first terminal of the drive module, a second electrode of the first transistor is connected to a second electrode of the second sub-transistor, a first electrode of the second sub-transistor is connected to a second electrode of the first sub-transistor, a first electrode of the first sub-transistor is connected to the control terminal of the drive module, a gate of the first transistor is connected to a first scan line, a gate of the second transistor is connected to a second scan line, and the coupling module is configured to couple the jump voltage to the second electrode of the first sub-transistor or the second electrode of the second sub-transistor. 6. The pixel circuit of claim 5 , wherein the jump voltage is a pulse voltage, the storage module comprises a first capacitor, the coupling module comprises a second capacitor, a first electrode of the first capacitor is connected to the fixed voltage, a second electrode of the first capacitor is connected to the control terminal of the drive module, a first electrode of the second capacitor is connected to the pulse voltage, a second electrode of the second capacitor is connected to the second electrode of the first sub-transistor, a first electrode of a third capacitor is configured to receive the pulse voltage or the fixed voltage, and a second electrode of the third capacitor is connected to the second electrode of the second sub-transistor. 7. The pixel circuit of claim 1 , wherein the second compensation module comprises a second transistor, a gate of the second transistor is connected to a second scan line, and a pulse of the pulse voltage is followed by a pulse on a signal transmitted by the second scan line. 8. The pixel circuit of claim 1 , wherein the jump voltage is a pulse voltage, and either the pulse voltage is jumped from a high level to a low level in a case where the second compensation module is turned off and is jumped from the low level to the high level before the light-emitting module is configured to emit light; or the pulse voltage is jumped from the low level to the high level in the case where the second compensation module is turned off and is jumped from the high level to the low level before the light-emitting module is configured to emit light. 9. The pixel circuit of claim 2 , wherein the first compensation module further comprises a third transistor, a gate of the third transistor is connected to the second scan line, a first electrode of the third transistor connected to the second electrode of the first transistor, and a second electrode of the third transistor is connected to a second electrode of the second transistor. 10. The pixel circuit of claim 1 , wherein the second compensation module comprises a second transistor, the pixel circuit further comprises a first initialization module and a second initialization module, the first initialization module comprises a fourth transistor, the second initialization module comprises a fifth transistor, a gate of the fourth transistor is connected to a third scan line, a first electrode of the fourth transistor is connected to an initialization signal line, a second electrode of the fourth transist

Assignees

Inventors

Classifications

  • Change or adaptation of the frame rate of the video stream · CPC title

  • Details of drivers for scan electrodes · CPC title

  • Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes · CPC title

  • Improving the luminance or brightness uniformity across the screen · CPC title

  • Details of timing specific for flat panels, other than clock recovery · CPC title

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What does patent US12170064B2 cover?
A pixel circuit, a driving method for a pixel circuit, and a display panel. The pixel circuit includes a drive module, a data write module, a first compensation module, a second compensation module, a light-emitting module, a storage module and a coupling module. The data write module is configured to write a voltage related to a data voltage to a control terminal of the drive module. The drive…
Who is the assignee on this patent?
Yungu Guan Tech Co Ltd
What technology area does this patent fall under?
Primary CPC classification G09G3/3233. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Dec 17 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 6 related publications on this page (citations in our corpus or others sharing the same primary CPC).