Display substrate and display device

Patent metadata

Field	Value
Publication number	US-12167647-B2
Application number	US-201916977533-A
Country	US
Kind code	B2
Filing date	Nov 29, 2019
Priority date	Nov 29, 2019
Publication date	Dec 10, 2024
Grant date	Dec 10, 2024

Abstract

A display substrate and a display device are provided. The display substrate includes a base substrate, the base substrate includes a display region and a periphery region; a plurality of data signal transmission lines, a plurality of signal output pads, a plurality of signal input pads, and a plurality of test pads are located in the periphery region; a plurality of sub-pixels and a plurality of data lines are located in the display region; the plurality of data signal transmission lines are electrically connected with at least part of the plurality of data lines; the periphery region is provided with a plurality of electrostatic release elements located between the plurality of signal output pads and the plurality of test pads, each electrostatic release element is electrically connected with one data signal transmission line and is configured to release static electricity on the data signal transmission line.

First claim

What is claimed is:

1. A display substrate, comprising:
a base substrate, comprising a display region and a periphery region at least located at one side of the display region;
a plurality of sub-pixels, located in the display region;
a plurality of data lines, located in the display region, the plurality of data lines being electrically connected with the plurality of sub-pixels;
a plurality of data signal transmission lines, located in the periphery region, the plurality of data signal transmission lines being electrically connected with at least part of the plurality of data lines;
a plurality of signal output pads, located in the periphery region and located between the plurality of data lines and the plurality of data signal transmission lines, the plurality of signal output pads being electrically connected with the plurality of data lines, the plurality of data signal transmission lines being electrically connected with at least part of the plurality of signal output pads;
a plurality of signal input pads, located in the periphery region and located at a side of the plurality of signal output pads away from the display region;
a plurality of test pads, located between the plurality of signal output pads and the plurality of signal input pads, the plurality of test pads being connected with the plurality of data signal transmission lines, respectively, the plurality of test pads being configured to be connected with an external test device during a manufacturing process of the display substrate to detect the display substrate; and
a plurality of electrostatic release elements, located between the plurality of signal output pads and the plurality of test pads, the plurality of electrostatic release elements being connected with the plurality of data signal transmission lines, respectively, each of the plurality of electrostatic release elements being configured to release static electricity on the data signal transmission line that is connected with the electrostatic release element,
wherein the display substrate further comprises a signal input element, and orthographic projections of the plurality of electrostatic release elements on the base substrate are located within an orthographic projection of the signal input element on the base substrate,
wherein the plurality of signal output pads and the plurality of signal input pads are bonded with the signal input element, and the plurality of electrostatic release elements are closer to the base substrate than the signal input element.

2. The display substrate according to claim 1 , wherein
the electrostatic release element comprises a first thin film transistor, a second thin film transistor, a first signal line, and a second signal line,
the first thin film transistor is connected with one data signal transmission line of the plurality of data signal transmission lines and is connected with the first signal line, respectively, and
the second thin film transistor is connected with the data signal transmission line and the second signal line, respectively.

3. The display substrate according to claim 2 , wherein
the first thin film transistor comprises a first electrode and a second electrode, one of the first electrode and the second electrode is connected with the data signal transmission line, and the other one of the first electrode and the second electrode is connected with the first signal line; and
the second thin film transistor comprises a third electrode and a fourth electrode, one of the third electrode and the fourth electrode is connected with the data signal transmission line, and the other one of the third electrode and the fourth electrode is connected with the second signal line.

4. The display substrate according to claim 3 , wherein
the first thin film transistor further comprises a first gate electrode, one of the first electrode and the second electrode is connected with the first gate electrode in a short circuit; and
the second thin film transistor further comprises a second gate electrode, one of the third electrode and the fourth electrode is connected with the second gate electrode in a short circuit.

5. The display substrate according to claim 2 , wherein
the first thin film transistor further comprises a first semiconductor layer, the first electrode and the second electrode are electrically connected with the first semiconductor layer, respectively; and
the second thin film transistor further comprises a second semiconductor layer, the third electrode and the fourth electrode are electrically connected with the second semiconductor layer, respectively,
wherein
a width-to-length ratio of a channel of the first semiconductor layer is in a range of 0.2-0.5, and
a width-to-length ratio of a channel of the second semiconductor layer is in a range of 0.2-0.5.

6. The display substrate according to claim 2 , wherein
two first thin film transistors are provided, one of the two first thin film transistors is located at a side of the other one of the two first thin film transistors away from the display region; and
two second thin film transistors are provided, one of the two second thin film transistors is located at a side of the other one of the two second thin film transistors away from the display region.

7. The display substrate according to claim 4 , wherein the first thin film transistor and the second thin film transistor are connected through the data signal transmission line,
wherein the data signal transmission line is intersected with the first signal line and the second signal line, respectively.

8. The display substrate according to claim 1 , further comprising a plurality of multiplexers, wherein
a first end of each of the plurality of multiplexers is electrically connected with the data signal transmission line, and a second end of the multiplexer is electrically connected with at least two signal output pads of the plurality of signal output pads.

9. The display substrate according to claim 1 , wherein the plurality of signal output pads comprise a first signal output pad and a second signal output pad,
the first signal output pad and the second signal output pad are connected with two different signal lines, respectively, and
the first signal output pad is closer to the display region than the second signal output pad to the display region.

10. The display substrate according to claim 9 , wherein an included angle between the first signal output pad and the second signal output pad is greater than 90° and is smaller than or equal to 135°.

11. A display substrate, comprising:
a base substrate, comprising a display region and a periphery region at least located at one side of the display region;
a plurality of sub-pixels, located in the display region;
a plurality of data lines, located in the display region, the plurality of data lines being electrically connected with the plurality of sub-pixels;
a plurality of data signal transmission lines, located in the periphery region, the plurality of data signal transmission lines being electrically connected with at least part of the plurality of data lines;
a plurality of signal output pads, located in the periphery region and located between the plurality of data lines and the plurality of data signal transmission lines, the plurality of signal output pads being electrically connected with the plurality of data lines, the plurality of data signal transmission lines being electrically connected with at least part of the plurality of signal output pads;
a plurality of signal input pads, located in the periphery region and located at a side of the plurality of signal output pads away from the display region, the plurality o

Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd

Inventors

• Zhang Bo
• Ma Hongwei
• Dong Xiangdan
• Cheng Bo
• Wang Rong

Classifications

• H10P74/273

  Interconnections for measuring or testing, e.g. probe pads · CPC title

• H10K50/88

  Terminals, e.g. bond pads · CPC title

• H10K59/131 Primary

  Interconnections, e.g. wiring lines or terminals · CPC title

• H10D89/931 Primary

  characterised by the dispositions of the protective arrangements · CPC title

• H01L22/32

  Electricity · mapped topic