Array substrate and display panel

Patent metadata

Field	Value
Publication number	US-11296125-B2
Application number	US-201816758158-A
Country	US
Kind code	B2
Filing date	Mar 6, 2018
Priority date	Oct 24, 2017
Publication date	Apr 5, 2022
Grant date	Apr 5, 2022

Abstract

An array substrate, comprises: a plurality of test leads correspondingly connected to a plurality of signal lines respectively through an electrostatic protection circuit; a plurality of driving chip binding pads, which are correspondingly connected to the plurality of test leads respectively through driving signal leads, and are configured to input a driving signal sent from a driving chip to the plurality of signal lines through the plurality of test leads; and the electrostatic protection circuit, which comprises a first connection terminal electrically connected to the plurality of test leads, and a second connection terminal electrically connected to the plurality of signal lines.

First claim

What is claimed is:

1. An array substrate, comprising:
a display area;
a non-display area surrounding the display area;
a plurality of signal lines disposed in the display area and the non-display area;
at least one electrostatic protection circuit disposed in the non-display area;
a plurality of test leads disposed in the non-display area and correspondingly connected to the plurality of signal lines respectively through the electrostatic protection circuit; and
a plurality of driving chip binding pads, which are disposed in the non-display area, correspondingly connected to the plurality of test leads respectively through driving signal leads, and are configured to input a driving signal sent from a driving chip to the plurality of signal lines through the plurality of test leads;
wherein the electrostatic protection circuit comprises a first connection terminal electrically connected to the plurality of test leads, and a second connection terminal electrically connected to the plurality of signal lines, and the electrostatic protection circuit is configured to output an electrostatic current generated by the array substrate upon externally inputting a test signal and binding the drive chip.

2. The array substrate according to claim 1 , further comprising:
a plurality of test pads disposed in the non-display area, and respectively corresponding to and electrically connected to the plurality of test leads.

3. The array substrate according to claim 1 , wherein, in a first direction, at least two gate drivers are disposed in the non-display area which is on two sides of the display area;
the signal lines comprise data signal lines which are disposed in the display area and drive signal lines of the gate drivers in the non-display area, the signal lines are disposed in a second direction and the second direction is perpendicular to the first direction.

4. The array substrate according to claim 3 , wherein:
the plurality of test leads and the driving chip binding pads are disposed in the non-display area on one side of the display area in the second direction.

5. The array substrate according to claim 4 , wherein:
the plurality of test leads comprise a first portion of test leads and a second portion of test leads;
the data signal lines comprise a first portion of data signal lines and a second portion of data signal lines;
the drive signal lines comprise a first portion of drive signal lines and a second portion of drive signal lines; and
the first portion of test leads are respectively corresponding to and are electrically connected to the first portion of data signal lines and the first portion of drive signal lines, and the second portion of test leads are respectively corresponding to and are electrically connected to the second portion of data signal lines and the second portion of drive signal lines.

6. The array substrate according to claim 5 , wherein:
the first portion of test leads and the second portion of test leads are respectively disposed on two sides of the driving chip binding pads.

7. The array substrate according to claim 5 , wherein:
the number of the first portion of test leads and the number of the second portion of test leads are the same; and
the number of the first portion of data signal lines and the first portion of drive signal lines is the same as the number of the second portion of data signal lines and the second portion of drive signal lines.

8. The array substrate according to claim 3 , wherein the drive signal lines of the gate drivers comprise:
power lines, clock signal lines and trigger signal lines.

9. An array substrate, comprising:
a display area;
a non-display area surrounding the display area;
a plurality of signal lines disposed in the display area and the non-display area;
at least one electrostatic protection circuit disposed in the non-display area;
a plurality of test leads disposed in the non-display area and correspondingly connected to the plurality of signal lines respectively through the electrostatic protection circuit;
a plurality of driving chip binding pads, which are disposed in the non-display area, correspondingly connected to the plurality of test leads respectively through driving signal leads, and are configured to input a driving signal sent from a driving chip to the plurality of signal lines through the plurality of test leads; and
a plurality of test pads,
wherein the electrostatic protection circuit comprises a first connection terminal electrically connected to the plurality of test leads, and a second connection terminal electrically connected to the plurality of signal lines, and the electrostatic protection circuit is configured to output an electrostatic current generated by the array substrate upon externally inputting a test signal and binding the drive chip,
in a first direction, at least two gate drivers are disposed in the non-display area which is on two sides of the display area;
the signal lines comprise data signal lines which are disposed in the display area and drive signal lines of the gate drivers in the non-display area, the signal lines are disposed in a second direction and the second direction is perpendicular to the first direction, and
the test pads are respectively corresponding to and electrically connected to the plurality of test leads.

10. A display panel, comprising an opposing substrate and an array substrate, wherein:
the array substrate comprises:
a display area;
a non-display area surrounding the display area;
a plurality of signal lines disposed in the display area and the non-display area;
at least one electrostatic protection circuit disposed in the non-display area;
a plurality of test leads disposed in the non-display area and correspondingly connected to the plurality of signal lines respectively through the electrostatic protection circuit; and
a plurality of driving chip binding pads, which are disposed in the non-display area, correspondingly connected to the plurality of test leads respectively through driving signal leads, and are configured to input a driving signal sent from a driving chip to the plurality of signal lines through the plurality of test leads;
wherein the electrostatic protection circuit comprises a first connection terminal electrically connected to the plurality of test leads, and a second connection terminal electrically connected to the plurality of signal lines, wherein the electrostatic protection circuit is configured to output an electrostatic current generated by the array substrate upon externally inputting a test signal and binding the drive chip.

11. The display panel according to claim 10 , wherein the array substrate further comprises:
a plurality of test pads disposed in the non-display area, and respectively corresponding to and electrically connected to the plurality of test leads.

12. The display panel according to claim 10 , wherein the array substrate further comprises:
at least two gate drivers disposed in the non-display area on two sides of the display area in a first direction;
wherein the signal lines comprise data signal lines disposed in the display area and drive signal lines of the gate drivers disposed in the non-display area, wherein the signal lines are disposed in a second direction perpendicular to the first direction.

13. The display panel according to claim 12 , wherein:
the plurality of test leads and the driving chip binding pads are disposed in the non-display area on one side of the display area in the second direction.

14. The display panel according to claim 13 , wherein:
the plurality of test leads comprise a

Assignees

• Hkc Corp Ltd

Inventors

• Huang Beizhou

Classifications

• H10P74/273

  Interconnections for measuring or testing, e.g. probe pads · CPC title

• H10D89/931

  characterised by the dispositions of the protective arrangements · CPC title

• H10D89/921 Primary

  characterised by the configuration of the interconnections connecting the protective arrangements, e.g. ESD buses · CPC title

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/60 Primary

  wherein the TFTs are in active matrices · CPC title