Pixel and display device including the same

Patent metadata

Field	Value
Publication number	US-12167646-B2
Application number	US-202217709848-A
Country	US
Kind code	B2
Filing date	Mar 31, 2022
Priority date	Aug 9, 2021
Publication date	Dec 10, 2024
Grant date	Dec 10, 2024

Abstract

A pixel includes a light emitting element including an anode and a cathode, a first transistor connected between the anode and a first power line and switched by a voltage of a node, a second transistor connected between the first transistor connected to the first power line and a data line and switched by a write scan signal, a third transistor connected between the node and the anode and switched by a compensation scan signal, and an insulating layer covering the second and third transistors. A first groove is defined in a portion of the insulating layer adjacent to the third transistor.

First claim

What is claimed is:

1. A pixel, comprising:
a light emitting element including an anode and a cathode;
a first transistor connected between the anode and a first power line, wherein the first transistor is switched by a voltage of a node;
a second transistor connected between the first transistor connected to the first power line and a data line, wherein the second transistor is switched by a write scan signal;
a third transistor connected between the node and the anode, wherein the third transistor is switched by a compensation scan signal; and
an insulating layer covering the second and third transistors,
wherein a first groove is defined in a portion of the insulating layer adjacent to the third transistor.

2. The pixel of claim 1 , wherein the insulating layer includes:
a buffer layer disposed on a base substrate; and
first, second, third, fourth, and fifth insulating layers sequentially laminated on the buffer layer,
wherein the second transistor is disposed on the buffer layer,
wherein the second insulating layer is disposed on the second transistor,
wherein the third transistor is disposed on the third insulating layer, and
wherein the fifth insulating layer is disposed on the third transistor.

3. The pixel of claim 2 , wherein the first groove is defined through portions of the fourth and fifth insulating layers overlapping each other.

4. The pixel of claim 3 , wherein the third transistor includes:
a source electrode, a drain electrode, and an active between the source electrode and the drain electrode, wherein the source electrode, the drain electrode, and the active are disposed on the third insulating layer; and
a gate disposed on the fourth insulating layer,
wherein the fourth insulating layer is disposed on the third insulating layer to cover the source electrode, the drain electrode, and the active,
wherein the fifth insulating layer is disposed on the fourth insulating layer to cover the gate, and
wherein the first groove is defined on a portion of a semiconductor pattern which defines the source electrode or the drain electrode.

5. The pixel of claim 4 , wherein the first groove exposes the portion of the semiconductor pattern.

6. The pixel of claim 3 , wherein a second groove deeper than the first groove is defined in a portion of the insulating layer adjacent to the third transistor.

7. The pixel of claim 6 , wherein the second groove is defined through portions of the first, second, third, fourth, and fifth insulating layers overlapping each other.

8. The pixel of claim 7 , wherein a portion of an upper surface of the buffer layer is recessed by a predetermined depth to further define the second groove in the buffer layer.

9. The pixel of claim 6 , further comprising:
a sixth insulating layer disposed on the fifth insulating layer,
wherein the sixth insulating layer fills the first and second grooves.

10. The pixel of claim 2 , wherein a third groove is defined in a portion of the insulating layer adjacent to the second transistor.

11. The pixel of claim 10 , wherein the third groove is defined through portions of the first, second, third, fourth, and fifth insulating layers overlapping each other.

12. The pixel of claim 11 , wherein a portion of an upper surface of the buffer layer is recessed by a predetermined depth to further define the third groove in the buffer layer.

13. The pixel of claim 2 , wherein the first, second, third, fourth, and fifth insulating layers include inorganic layers.

14. The pixel of claim 2 , wherein a thickness of each of the third and fifth insulating layers are greater than a thickness of each of the buffer layer and the first, second, and fourth insulating layers.

15. The pixel of claim 2 , wherein each of the third and fifth insulating layers includes a plurality of inorganic insulating layers including different materials from each other and laminated with each other.

16. A pixel, comprising:
a light emitting element including an anode and a cathode;
a first transistor connected between the anode and a first power line, wherein the first transistor is switched by a voltage of a node;
a second transistor connected between the first transistor connected to the first power line and a data line, wherein the second transistor is switched by a write scan signal;
a third transistor connected between the node and the anode, wherein the third transistor is switched by a compensation scan signal; and
an insulating layer covering the second and third transistors,
wherein a plurality of grooves are defined in portions of the insulating layer adjacent to the second and third transistors, and
wherein a depth of one of the grooves is different from a depth of another of the grooves.

17. The pixel of claim 16 ,
wherein a first groove and a second groove are defined in portions of the insulating layer adjacent to the third transistor,
wherein a third groove is defined in a portion of the insulating layer adjacent to the second transistor, and
wherein a depth of each of the second groove and the third groove is deeper than a depth of the first groove.

18. The pixel of claim 17 , wherein the insulating layer includes:
a buffer layer disposed on a base substrate; and
first, second, third, fourth, and fifth insulating layers sequentially laminated on the buffer layer,
wherein the second transistor is disposed on the buffer layer,
wherein the second insulating layer is disposed on the second transistor,
wherein the third transistor is disposed on the third insulating layer, and
wherein the fifth insulating layer is disposed on the third transistor.

19. The pixel of claim 18 ,
wherein the first groove is defined through portions of the fourth and fifth insulating layers overlapping each other, and
wherein the second groove and the third groove are defined through portions of the first, second, third, and fourth, and fifth insulating layers overlapping each other.

20. A display device, comprising:
a pixel,
wherein the pixel includes:
a light emitting element including an anode and a cathode;
a first transistor connected between the anode and a first power line, wherein the first transistor is switched by a voltage of a node;
a second transistor connected between the first transistor connected to the first power line and a data line, wherein the second transistor is switched by a write scan signal;
a third transistor connected between the node and the anode, wherein the third transistor is switched by a compensation scan signal; and
an insulating layer covering the second and third transistors,
wherein a first groove and a second groove are defined in portions of the insulating layer adjacent to the third transistor, and
wherein the first groove and the second groove have different depths from each other.

Assignees

• Samsung Display Co Ltd

Inventors

• Choi Wonwoo
• Kim Jaechung
• Lim Jaeik
• Kim In-Bae

Classifications

• H10D86/423

  comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10K59/131

  Interconnections, e.g. wiring lines or terminals · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• H10K59/123

  Connection of the pixel electrodes to the thin film transistors [TFT] · CPC title