Organic light emitting diode display
US-2019198806-A1 · Jun 27, 2019 · US
US12167641B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-12167641-B2 |
| Application number | US-202318096623-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jan 13, 2023 |
| Priority date | Feb 24, 2020 |
| Publication date | Dec 10, 2024 |
| Grant date | Dec 10, 2024 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
A display panel includes a substrate, a first thin film transistor including a first semiconductor layer and a first gate electrode, a data line extending in a first direction, a scan line extending in a second direction, a second thin film transistor electrically connected to the data line and including a second semiconductor layer and a second gate electrode, a third thin film transistor including a third semiconductor layer and a first upper gate electrode arranged on the third semiconductor layer, a node connection line electrically connecting the first thin film transistor and the third thin film transistor, and a shield line located between the data line and the node connection line in a plan view and including the same material as the first upper gate electrode of the third thin film transistor. The first semiconductor layer includes a silicon semiconductor, and the third semiconductor layer includes an oxide semiconductor.
Opening claim text (preview).
What is claimed is: 1. A display apparatus comprising a display area in which a plurality of pixels are disposed and a peripheral area disposed outside the display area, each of the plurality of pixels comprising: a driving transistor comprising a silicon semiconductor; a first transistor connected to a data line and the driving transistor and comprising a silicon semiconductor; and a second transistor connected to a gate electrode of the driving transistor and the silicon semiconductor of the driving transistor, wherein the second transistor comprises a first gate electrode, a second gate electrode and an oxide semiconductor disposed between the first gate electrode and the second gate electrode, and wherein one end of the oxide semiconductor of the second transistor is connected to the gate electrode of the driving transistor and the other end of the oxide semiconductor of the second transistor is connected to the silicon semiconductor of the driving transistor. 2. The display apparatus of claim 1 , wherein the first gate electrode and the second gate electrode of the second transistor are electrically connected each other through a contact hole. 3. The display apparatus of claim 1 , further comprising a first capacitor comprising a first electrode connected to the gate electrode of the driving transistor and a second electrode overlapping the first electrode and connected to a first voltage line. 4. The display apparatus of claim 1 , further comprising a second capacitor comprising a third electrode connected to a gate electrode of the first transistor and a fourth electrode connected to the gate electrode of the driving transistor. 5. The display apparatus of claim 4 , wherein the third electrode of the second capacitor and the gate electrode of the driving transistor are disposed on a same layer, and wherein the fourth electrode of the second capacitor and the oxide semiconductor of the second transistor are disposed on a same layer. 6. The display apparatus of claim 4 , further comprising a scan line connected to the second transistor, wherein the data line extends in a first direction and the scan line extends in a second direction perpendicular to the first direction, and wherein the third electrode and the fourth electrode cross the scan line in the first direction. 7. The display apparatus of claim 1 , further comprising a third transistor connected between the gate electrode of the driving transistor and a second voltage line, and wherein the third transistor comprises a first gate electrode, a second gate electrode and an oxide semiconductor disposed between the first gate electrode and the second gate electrode. 8. The display apparatus of claim 7 , wherein the first gate electrode and the second gate electrode of the third transistor are electrically connected each other through a contact hole. 9. The display apparatus of claim 1 , further comprising a shield line disposed between the data line and a node connection line electrically connecting the driving transistor and the second transistor in a plan view. 10. The display apparatus of claim 9 , wherein the second gate electrode of the second transistor and the shield line comprise a same material. 11. The display apparatus of claim 9 , wherein the shield line receives a constant voltage. 12. The display apparatus of claim 9 , wherein the shield line extends in an extension direction of the data line. 13. The display apparatus of claim 1 , further comprising: a driving voltage line extending in a first direction; a node connection line electrically connecting the driving transistor and the second transistor and extending in the first direction; and a shield line electrically connected to the driving voltage line and located between the data line and the node connection line in a plan view. 14. The display apparatus of claim 1 , further comprising: a light emitting diode; a third transistor connected between the gate electrode of the driving transistor and a second voltage line; a fifth transistor connected between the driving transistor and the light emitting diode; and a sixth transistor connected between the light emitting diode and the second voltage line. 15. The display apparatus of claim 1 , wherein the silicon semiconductor of the driving transistor has a bent portion.
having different architectures, e.g. having both top-gate and bottom-gate TFTs · CPC title
comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title
wherein the TFTs are in active matrices · CPC title
Interconnections, e.g. scanning lines · CPC title
the pixel elements being capacitors · CPC title
Related publications grouped by family.
Answers are generated from the same data shown on this page.