Semiconductor structure and a manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-12166133-B2
Application number	US-202117456591-A
Country	US
Kind code	B2
Filing date	Nov 25, 2021
Priority date	Nov 23, 2020
Publication date	Dec 10, 2024
Grant date	Dec 10, 2024

Abstract

A semiconductor structure includes: a substrate; a gate structure located on the substrate, wherein the gate structure comprises a first conductive layer, a barrier layer and a second conductive layer which are stacked in sequence; wherein the first conductive layer includes a first polysilicon layer, a first metal layer and a second polysilicon layer, wherein the first polysilicon layer is adjacent to the substrate and the second polysilicon layer is contiguous to the barrier layer; and wherein the first metal layer is located between the first polysilicon layer and the second polysilicon layer. The gate structure of the embodiments of the application has a straight profile and an excellent electrical performance.

First claim

What is claimed is:

1. A semiconductor structure comprising:
a substrate; and
a gate structure located on the substrate, wherein the gate structure comprises a first conductive layer, a barrier layer and a second conductive layer which are stacked in sequence;
wherein the first conductive layer comprises at least two polysilicon layers, and at least one metal layer, wherein a bottom layer of the at least two polysilicon layers is adjacent to the substrate, and a top layer of the at least two polysilicon layers is contiguous to the barrier layer; and adjacent polysilicon layers are provided with one metal layer; and
the first conductive layer has a total thickness of 23 nm to 50 nm;
each polysilicon layer has a same thickness and has a thickness of 9 nm to 15 nm, and each metal layer has a same thickness, and a thickness of each metal layer is from 0.5 nm to 1.5 nm.

2. The semiconductor structure of claim 1 , further comprising a gate dielectric layer located between the gate structure and the substrate.

3. The semiconductor structure of claim 1 , wherein a material of the first metal layer comprises titanium nitride or tantalum nitride.

4. The semiconductor structure of claim 1 , further comprising an insulating cap layer on the gate structure.

5. The semiconductor structure of claim 1 , wherein
the first conductive layer comprises a first polysilicon layer, a second polysilicon layer and a first metal layer located between the first polysilicon layer and the second polysilicon layer; and
the first polysilicon layer and the second polysilicon layer are doped with P-type ions or N-type ions.

6. The semiconductor structure of claim 5 , wherein a concentration of doped ions in the first polysilicon layer differs from that in the second polysilicon layer.

7. The semiconductor structure of claim 1 , wherein the first conductive layer further comprises a third polysilicon layer, a second metal layer, a first polysilicon layer, a first metal layer, and a second polysilicon layer which are sequentially stacked, wherein the third polysilicon layer is adjacent to the substrate, and the second metal layer is located between the third polysilicon layer and the first polysilicon layer.

8. The semiconductor structure of claim 7 , wherein the first metal layer and the second metal layer have the same materials and thickness.

9. The semiconductor structure of claim 1 , wherein the barrier layer has a thickness of 5 nm to 10 nm.

10. The semiconductor structure of claim 1 , wherein the second conductive layer has a thickness of 20 nm to 40 nm.

11. A manufacturing method of a semiconductor structure, comprising:
providing a substrate;
sequentially forming on the substrate an initial first conductive layer, an initial barrier layer and an initial second conductive layer, which in turn constitute an initial gate structure; wherein the initial first conductive layer comprises at least two initial first polysilicon layers, at least one initial metal layer, with a bottom layer of the at least two initial first polysilicon layers located adjacent to the substrate and a top layer of the at least two initial second polysilicon layers located contiguous to the initial barrier layer; and wherein adjacent initial polysilicon layers are provided with one initial metal layer;
forming a patterned mask layer on the initial gate structure; and
etching the initial first conductive layer, the initial barrier layer and the initial second conductive layer with the patterned mask layer as a mask to form a first conductive layer, a barrier layer and a second conductive layer; wherein the first conductive layer, the barrier layer and the second conductive layer constitute a gate structure; and the first conductive layer comprises at least two polysilicon layers, and at least one metal layer;
the first conductive layer has a total thickness of 23 nm to 50 nm;
each polysilicon layer has a same thickness and has a thickness of 9 nm to 15 nm, and each metal layer has a same thickness, and a thickness of each metal layer is from 0.5 nm to 1.5 nm.

12. The manufacturing method of claim 11 , wherein the first metal layer is formed by an atomic layer deposition process.

13. The manufacturing method of claim 11 , wherein
the first conductive layer comprises a first polysilicon layer, a second polysilicon layer and a first metal layer located between the first polysilicon layer and the second polysilicon layer; and
in a process of etching the initial second polysilicon layer, an etching selection ratio of the initial second polysilicon layer to the initial first metal layer is higher than 100:1; and in the process of etching the initial first metal layer, an etching selection ratio of the initial first metal layer to the initial first polysilicon layer is higher than 10:1.

14. The manufacturing method of claim 11 , wherein before the initial gate structure is formed, the method further comprises:
forming an initial gate dielectric layer on the substrate, wherein the initial gate structure is located on the initial gate dielectric layer; and
after the initial gate structure is formed, the method further comprises: forming an initial insulating cap layer which covers the initial gate structure.

15. The manufacturing method of claim 14 , wherein after the patterned mask layer is formed, the method further comprises: etching the initial insulating cap layer and the initial gate dielectric layer with the patterned mask layer as a mask to form an insulating cap layer and a gate dielectric layer.

16. The manufacturing method of claim 15 , wherein,
an etching gas of the initial insulating cap layer is filled into the chamber, and is discharged after completion of a first etching;
another etching gas of the initial second conductive layer is filled into the chamber, and is discharged after completion of a second etching; and
the first etching and the second etching are iterated until the initial barrier layer, the initial first conductive layer and initial gate dielectric layer are all etched.

17. The manufacturing method of claim 11 , wherein after each initial polysilicon layer is formed, ion implantation is performed on the each initial polysilicon layer.

Assignees

• Changxin Memory Tech Inc

Inventors

• Long Qiang

Classifications

• H10P50/263

  of silicon-containing layers · CPC title

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H10P32/302

  Doping polycrystalline silicon or amorphous silicon layers · CPC title

• H10P14/3456

  Polycrystalline · CPC title

• H10P14/418

  the conductive layers comprising transition metals · CPC title