Ternary memory cell and memory device comprising same

Patent metadata

Field	Value
Publication number	US-12165699-B2
Application number	US-202017424490-A
Country	US
Kind code	B2
Filing date	Apr 3, 2020
Priority date	Apr 5, 2019
Publication date	Dec 10, 2024
Grant date	Dec 10, 2024

Abstract

In a memory device including a ternary memory cell, the ternary memory cell may include: a first inverter and a second inverter cross-coupled in a first node and a second node and including a pull-up device and a pull-down device configured to have a constant current pass therethrough upon turn-off; a first read transistor and a first write transistor which are connected to each other in parallel between the first node and a first bit line; and a second read transistor and a second write transistor which are connected to each other in parallel between the second node and a second bit line, wherein the first read transistor and the second read transistor may have a read access current, which is less than or equal to the constant current, pass therethrough in response to an activated read word line.

First claim

The invention claimed is:

1. A method of operating a memory device comprising a ternary memory cell, the method comprising:
providing a first inverter and a second inverter cross-coupled in a first node and a second node and comprising a pull-up device and a pull-down device configured to have a constant current pass therethrough upon turn-off;
providing a first read transistor and a first write transistor that are connected to each other in parallel between the first node and a first bit line;
providing a second read transistor and a second write transistor that are connected to each other in parallel between the second node and a second bit line;
causing a read access current, which is less than or equal to the constant current, to pass through the first read transistor and the second read transistor in response to an activated read word line; and
storing a ternary value by causing the ternary memory cell to be in a state corresponding to one of the following states: a first state in which both of the pull-up device and the pull-down device are turned off, a second state in which the pull-up device is turned on and the pull-down device is turned off, and a third state in which the pull-up device is turned off and the pull-down device is turned on, wherein:
the pull-up device and the pull-down device are configured to have a first current pass therethrough in the first state and a second current greater than the first current pass therethrough in the second state and the third state, and
wherein the first read transistor and the second read transistor have greater threshold voltages than those of the first write transistor and the second write transistor.

2. The method of claim 1 , further comprising:
with a page buffer, determining a ternary value based on a difference between a first voltage of the first bit line and a second voltage of the second bit line in a read operation.

3. The method of claim 1 , wherein the first write transistor and the second write transistor are configured to have a write access current, which is greater than or equal to the constant current, pass therethrough in response to an activated write word line.

4. The method of claim 1 , wherein the first read transistor and the second read transistor have sizes less than sizes of the first write transistor and the second write transistor.

5. The method of claim 1 , wherein the ternary memory cell state is in the first state, the method further comprising:
causing the memory cell to be in the second state.

6. The method of claim 5 , further comprising:
causing the memory cell to be in the third state.

7. The method of claim 1 , wherein the ternary memory cell is in the first state, the method further comprising:
causing the ternary memory cell to be in the third state.

8. The method of claim 1 , wherein the ternary memory cell state is in the second state or the third state, the method further comprising:
causing the ternary memory cell to be in a different state being a different one of the first state, second state, or third state than the ternary memory cell.

9. A method of operating a memory device comprising a ternary memory cell storing a ternary value, the method comprising:
providing a first inverter and a second inverter cross-coupled in a first node and a second node and comprising a pull-up device and a pull-down device configured to have a constant current pass therethrough upon turn-off;
providing a first access transistor connected to the first node and a first bit line;
providing a second access transistor connected to the second node and a second bit line;
causing a row decoder configured to provide a read word line voltage to each of the first access transistor and the second access transistor such that a read access current which is less than or equal to the constant current passes through the first access transistor and the second access transistor in a read operation; and
storing a ternary value in the ternary memory cell by causing the ternary memory cell to be in a state corresponding to one of the following: a first state in which both of the pull-up device and the pull-down device are turned off, a second state and a third state in which one of the pull-up device and the pull-down device is turned on and the other is turned off, wherein:
the pull-up device and the pull-down device are configured to have a first current pass therethrough in the first state and have a second current, which is greater than the first current, pass therethrough in the second state and the third state, and
wherein the row decoder is configured to provide a write word line voltage to each of the first access transistor and the second access transistor such that a write access current having a magnitude greater than or equal to the second current passes through the first access transistor and the second access transistor in a write operation.

10. The method of claim 9 , further comprising:
with a page buffer, determining a ternary value based on a difference between a first voltage of the first bit line and a second voltage of the second bit line in the read operation.

11. The method of claim 9 , wherein the ternary memory cell state is in the first state, the method further comprising:
causing the memory cell to be in the second state.

12. The method of claim 11 , further comprising:
causing the memory cell to be in the third state.

13. The method of claim 9 , wherein the ternary memory cell is in the first state, the method further comprising:
causing the ternary memory cell to be in the third state.

14. The method of claim 9 , wherein the ternary memory cell state is in the second state or in the third state, the method further comprising:
causing the ternary memory cell to be in a different state being a different one of the first state, second state, or third state than the ternary memory cell.

15. A memory device comprising:
a page buffer comprising a latch and a read circuit comprising ternary logic devices, the page buffer being situated to determine a ternary value stored in a ternary memory cell based on a voltage difference between a first bit line and a second bit line of the ternary memory cell; and
the ternary memory cell, the ternary memory cell being coupled to the page buffer and comprising:
a first inverter and a second inverter cross-coupled in a first node and a second node and comprising a pull-up device and a pull-down device configured to have a constant current pass therethrough upon turn-off;
a first read transistor and a first write transistor which are connected to each other in parallel between the first node and the first bit line, the first bit line situated to be precharged by the ternary logic devices of the read circuit; and
a second read transistor and a second write transistor which are connected to each other in parallel between the second node and the second bit line, the second bit line situated to be precharged by the ternary logic devices of the read circuit,
wherein:
the first read transistor and the second read transistor are configured to have a read access current, which is less than or equal to the constant current, pass therethrough in response to an activated read word line,
the ternary memory cell is configured to store a ternary value corresponding to a first state in which both of the pull-up device and the pull-down device are turned off, a second state and a third state in which one of the pull-up device and the pull-down device is turned on and the other is turned off,
the pull-up device and the pull-down device are configured to have a first curren

Assignees

• Ulsan Nat Inst Science & Tech Unist

Inventors

• Kim Kyung Rok
• Jeong Jae Won
• Choi Young Eun

Classifications

• H03K19/01721 Primary

  by means of a pull-up or down element · CPC title

• G11C11/412

  using field-effect transistors only · CPC title

• G11C11/4094

  Bit-line management or control circuits · CPC title

• G11C11/4085

  Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge · CPC title

• H03K19/09429

  one of the states being the high impedance or floating state · CPC title