Method and apparatus for selective input/output (IO) terminal safe-stating for independent on-chip applications

Patent metadata

Field	Value
Publication number	US-12164369-B2
Application number	US-202318152217-A
Country	US
Kind code	B2
Filing date	Jan 10, 2023
Priority date	Oct 29, 2022
Publication date	Dec 10, 2024
Grant date	Dec 10, 2024

Abstract

A system-on-chip (SoC) may include a plurality of terminals and a plurality of terminal controllers. Each terminal controller is configured to selectively disable a terminal. An SoC be configured to execute at least one application. An SoC may include a memory configured to store a plurality of terminal masks. Each terminal mask identifies a subset of the plurality of terminals to be disabled. An SoC may include a fault collection and reaction system configured to transmit, to the plurality of terminal controllers, a fault indication signal in response to an error in a corresponding application. Each terminal controller is further configured to determine, based on a fault indication signal and a value in a terminal mask, whether the terminal corresponding to the terminal controller is to be disabled, and when the terminal corresponding to the terminal controller is to be disabled, disable the terminal.

First claim

What is claimed is:

1. A system-on-chip (SoC), comprising:
a plurality of terminals;
a plurality of terminal controllers, each terminal controller in the plurality of terminal controllers being configured to selectively disable a terminal of the plurality of terminals;
a plurality of processor cores, wherein each processor core is configured to execute at least one application;
a memory configured to store a plurality of terminal masks, wherein each terminal mask in the plurality of terminal masks is associated with a reaction core and identifies a subset of the plurality of terminals to be disabled; and
a fault collection and reaction system coupled to the plurality of processor cores, wherein the fault collection and reaction system includes:
a plurality of reaction cores, wherein each reaction core of the plurality of reaction cores is configured to transmit a fault indication signal in response to an error in a corresponding application; and
a controller configured to:
receive a first fault indication signal from a first reaction core of the plurality of reaction cores;
transmit the first fault indication signal to the plurality of terminal controllers, wherein each terminal controller is further configured to:
determine, based on the first fault indication signal and a value in a first terminal mask, whether the terminal corresponding to the terminal controller is to be disabled, wherein the first terminal mask is associated with the first reaction core, and
when the terminal corresponding to the terminal controller is to be disabled, disable the terminal.

2. The SoC of claim 1 , wherein the first terminal mask includes a first array having a number of values equal to a number of terminals in the plurality of terminals, wherein each value in the first array is associated with a terminal of the plurality of terminals.

3. The SoC of claim 2 , wherein values in the first array that are associated with terminals in a first subset of terminals have a first Boolean value and values in the first array that are associated with terminals that are not in the first subset of terminals have a second Boolean value.

4. The SoC of claim 3 , wherein each terminal controller in the plurality of terminal controllers includes a first input configured to receive an input from the first terminal mask and a second input configured to receive the first signal indicative of the first fault indication.

5. The SoC of claim 1 , wherein the controller is configured to:
receive a second fault indication signal from a second reaction core of the plurality of reaction cores; and
transmit the second fault indication signal to the plurality of terminal controllers, wherein each terminal controller is further configured to:
determine, based on the second fault indication signal and a value in a second terminal mask, whether the terminal corresponding to the terminal controller is to be disabled, wherein the second terminal mask is associated with the second reaction core, and
when the terminal corresponding to the terminal controller is to be disabled, disable the terminal.

6. The SoC of claim 1 , wherein the plurality of terminals includes signal pins, contact pads, and/or solder balls.

7. A system-on-chip (SoC), comprising:
a plurality of terminals;
a plurality of terminal controllers, each terminal controller in the plurality of terminal controllers being configured to selectively disable a terminal of the plurality of terminals;
a processor configured to execute a plurality of applications; and
a fault collection and reaction system configured to:
detect a first fault indication for a first application of the plurality of applications, and
responsive to the first fault indication, transmit a first signal indicative of the first fault indication to the plurality of terminal controllers to disable an operation of a first subset of the plurality of terminals, wherein the first subset includes terminals that are used by the first application and the first subset does not include terminals that are not used by the first application; and

a memory configured to store a plurality of terminal masks including a first terminal mask that is associated with the first fault indication and identifies the first subset of the plurality of terminals to be disabled.

8. The SoC of claim 7 , wherein the first terminal mask includes a first array having a number of values equal to a number of terminals in the plurality of terminals, wherein each value in the first array is associated with a terminal of the plurality of terminals.

9. The SoC of claim 8 , wherein values in the first array that are associated with terminals in the first subset of terminals have a first Boolean value and values in the first array that are associated with terminals that are not in the first subset of terminals have a second Boolean value.

10. The SoC of claim 9 , wherein each terminal controller in the plurality of terminal controllers includes a first input configured to receive a first value from the first terminal mask and a second input configured to receive the first signal indicative of the first fault indication.

11. The SoC of claim 10 , wherein each terminal controller is configured to disable the terminal associated with the terminal controller when the first input is set to the first Boolean value and the second input receives the first signal.

12. The SoC of claim 11 , wherein the controller is configured to:
detect a second fault indication for a second application of the plurality of applications, and
responsive to the second fault indication, transmit a second signal indicative of the second fault indication to the plurality of terminal controllers to disable an operation of a second subset of the plurality of terminals, wherein the second subset includes terminals that are used by the second application and the second subset does not include terminals that are not used by the second application.

13. The SoC of claim 12 , wherein the memory includes a second terminal mask that is associated with the second fault indication and identifies the second subset of the plurality of terminals to be disabled, the second terminal mask including a second array having a second number of values equal to the number of terminals in the plurality of terminals, wherein each value in the first array is associated with a terminal of the plurality of terminals.

14. The SoC of claim 13 , wherein values in the second array that are associated with terminals in the second subset of terminals have the first Boolean value and values in the second array that are associated with terminals that are not in the second subset of terminals have the second Boolean value.

15. The SoC of claim 14 , wherein each terminal controller in the plurality of terminal controllers includes a third input configured to receive a second value from the second terminal mask and a fourth input configured to receive the second signal indicative of the second fault indication.

16. The SoC of claim 15 , wherein each terminal controller is configured to disable the terminal associated with the terminal controller when the third input is set to the first Boolean value and the fourth input receives the second signal.

17. The SoC of claim 7 , wherein the plurality of terminals includes one or more of signal pins, contact pads, and solder balls.

18. A method, comprising:
receiving a signal from a reaction core indicating a fault in a first application executed by a processor;
accessing a memory which stores a plurality of terminal masks i

Assignees

• Nxp Bv

Inventors

• Sethi Ankush
• Kaul Rohit Kumar
• Jain Aarul

Classifications

• G06F11/0772

  Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers · CPC title

• G06F11/0724

  in a multiprocessor or a multi-core unit (multiprocessors per se G06F15/80) · CPC title

• G06F11/0751

  Error or fault detection not based on redundancy (power supply failures G06F1/30; network fault management H04L41/06) · CPC title

• G06F11/0793 Primary

  Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40) · CPC title