Expitaxial semiconductor/superconductor heterostructures

Patent metadata

Field	Value
Publication number	US-12161052-B2
Application number	US-201916978415-A
Country	US
Kind code	B2
Filing date	Mar 6, 2019
Priority date	Mar 6, 2018
Publication date	Dec 3, 2024
Grant date	Dec 3, 2024

Abstract

Solid-state devices including a layer of a superconductor material epitaxially grown on a crystalline high thermal conductivity substrate, the superconductor material being one of TiNx, ZrNx, HfNx, VNx, NbNx, TaNx, MoNx, WNx, or alloys thereof, and one or more layers of a semiconducting or insulating or metallic material epitaxially grown on the layer of superconductor material, the semiconducting or insulating material being one of a Group III N material or alloys thereof or a Group 4b N material or SiC or ScN or alloys thereof.

First claim

What is claimed is:

1. A solid-state device comprising:
at least one layer of a superconductor material epitaxially grown on a crystalline high thermal conductivity substrate; the superconductor material being one of TiNx, ZrNx, HfNx, VNx, NbNx, TaNx, MoNx, WNx, or alloys thereof; and
one or more layers of a semiconducting or insulating or metallic material epitaxially grown on one of the at least one layer of superconductor material; the semiconducting or insulating material being one of a Group III-N (nitride) material or alloys thereof or a Group 4b-N (nitride), or transition metal nitride material, or SiC or alloys thereof; wherein the one or more layers comprise at least two layers, one of said at least two layers being a semiconducting layer; wherein the at least two layers comprise a semiconductor heterostructure and a semiconductor quantum well heterostructure; and wherein the semiconductor heterostructure comprises a transistor.

2. The solid-state device of claim 1 , wherein the crystalline high thermal conductivity substrate is one of GaN, AlN, 4H- and 6H-SiC, AlScN, GaScN, 3C-SiC or Si.

3. The solid-state device of claim 1 , wherein the solid-state device also comprises a metal contact disposed on a surface of a last layer of semiconducting material, said surface being opposite a surface disposed on the layer of the superconductor material.

4. The solid-state device of claim 1 , wherein the one or more layers that comprise a semiconductor heterostructure are epitaxially grown on an exposed one of the at least one layer of superconductor material.

5. The solid-state device of claim 1 further comprising metal contacts for each of source, drain and gate of the transistor, and a metal layer through a via connecting the layer of superconductor material to one of the metal contacts.

6. A solid-state device comprising:
a layer of a superconductor material epitaxially grown on a crystalline high thermal conductivity substrate; the superconductor material being one of TiNx, ZrNx, HfNx, VNx, NbNx, TaNx, MoNx, WNx, or alloys thereof; and
one or more layers of a semiconducting or insulating or metallic material epitaxially grown on the layer of superconductor material; the semiconducting or insulating material being one of a Group III-N (nitride) material or alloys thereof or a Group 4b-N (nitride), or transition metal nitride material, or SiC or alloys thereof; wherein the one or more layers comprise at least two layers, one of said at least two layers being a semiconducting layer; wherein the at least two layers comprise a semiconductor heterostructure; wherein at least a portion of the semiconductor heterostructure forms a transistor; wherein the transistor is, at one surface, etched down to a portion of the crystalline high thermal conductivity substrate; wherein the solid-state device further comprises another layer of the superconductor material, said another layer being epitaxially grown on said portion of the crystalline high thermal conductivity substrate in a nanowire meander pattern and operatively electrically connected to one of a gate or a source of the transistor.

7. The solid-state device of claim 6 , wherein said another layer is epitaxially grown on said one surface and makes an electrical connection to one of the gate or the source of transistor.

8. The solid-state device of claim 1 , wherein the one or more layers also comprise a first layer of the semiconducting or insulating or metallic material; and wherein the solid-state device further comprises another layer of the superconductor material epitaxially grown on the one layer of the semiconducting or insulating material.

9. The solid-state device of claim 8 wherein said another layer of the superconductor material is etched in order to form a pattern of linear elements extending along one of two orthogonal axes in a plane; and wherein said layer of the superconductor material is etched in order to form a pattern of linear elements extending along another one of the two orthogonal axes in the plane.

10. The solid-state device of claim 1 , wherein the semiconductor heterostructure is a Group III-N semiconductor heterostructure; and wherein the one or more layers are N-polar layers.

11. The solid-state device of claim 1 , wherein the one or more layers are N-polar layers.

12. The solid state device of claim 1 , wherein said at least one layer comprises one or more structures epitaxially grown on a first layer of the at least one layer of the superconductor material, the one or more structures comprising an insulator layer and another layer of the superconductor material epitaxially grown on the insulator layer; and wherein the one or more structures are epitaxially grown on the layer of superconductor material; and wherein said one or more layers are epitaxially grown on a last layer of the superconductor material from the one or more structures.

13. The solid-state device of claim 12 , wherein the semiconducting or insulating material is one of a Group III-N (nitride) material or alloys thereof or a Group 4b-N (nitride), or transition metal nitride material; and wherein the one or more layers are N-polar layers.

14. The solid-state device of claim 13 , wherein the one or more structures comprise two structures.

15. The solid-state device of claim 6 , wherein the semiconducting or insulating material is one of a Group III-N (nitride) material or alloys thereof or a Group 4b-N (nitride), or transition metal nitride material; and wherein the one or more layers are N-polar layers.

Assignees

• Univ Cornell
• Us Gov Sec Navy
• Govmt Of U S —Navy

Inventors

• Yan Rusen
• Khalsa Guru Bahadur Singh
• Wright John
• Xing H Grace
• Jena Debdeep
• Katzer D Scott
• Nepal Neeraj
• Downey Brian P
• Meyer David J

Classifications

• H10W20/064

  by modifying the conductivity of conductive parts, e.g. by alloying · CPC title

• H10P14/3416

  Nitrides · CPC title

• H10P14/3216

  Nitrides · CPC title

• H10P14/3251

  consisting of three or more layers · CPC title

• H10P14/3241

  being conductive materials · CPC title