Integrated circuit with output driver that compensates for supply voltage variations

Patent metadata

Field	Value
Publication number	US-12160237-B2
Application number	US-202217843693-A
Country	US
Kind code	B2
Filing date	Jun 17, 2022
Priority date	Jun 24, 2021
Publication date	Dec 3, 2024
Grant date	Dec 3, 2024

Abstract

An integrated circuit includes an output pad, and I/O driver that drives data to the output pad, and a predriver that controls the I/O driver. The integrated circuit includes maximum voltage generator that receives a first supply voltage and a second supply voltage and outputs to the predriver a maximum voltage corresponding to the higher of the first supply voltage and the second supply voltage.

First claim

The invention claimed is:

1. An integrated circuit, comprising:
an output pad;
an output driver coupled to the output pad;
a predriver block coupled to the output driver;
a maximum voltage generator coupled to the predriver block, wherein the maximum voltage generator is configured to receive a core supply voltage and an input/output (I/O) supply voltage, to compare the core supply voltage to the I/O supply voltage, to select a maximum voltage corresponding to a higher of the core supply voltage and the I/O supply voltage based on the comparison, and to supply the maximum voltage to the predriver block; and
a core including a plurality of core transistors powered by the core supply voltage, wherein:
the predriver block is coupled to the core, receives data from the core and controls the output driver to output the data on the output pad;
the predriver block includes a first level shifter that receives the maximum voltage and the data and shifts the data to a level of the maximum voltage; and
the predriver block includes a first predriver coupled to the first level shifter, wherein the first predriver receives the level shifted data from the first level shifter and receives the maximum voltage and controls the output driver based on the level shifted data.

2. The integrated circuit of claim 1 , wherein the predriver block includes a second level shifter that receives the maximum voltage and complimentary data from the core and shifts the complimentary data to a level of the maximum voltage, wherein the complimentary data is a logical compliment of the data.

3. The integrated circuit of claim 2 , wherein the predriver block includes a second predriver coupled to the second level shifter, wherein the second predriver receives the level shifted complimentary data from the second level shifter and receives the maximum voltage and controls the output driver based on the complimentary level shifted data.

4. The integrated circuit of claim 3 , wherein the output driver includes:
a PMOS transistor having a source terminal coupled the I/O supply voltage, a drain terminal coupled to the output pad, and a gate terminal coupled to the first predriver; and
an NMOS transistor having a source terminal coupled to ground, a drain terminal coupled to the output pad, and a gate terminal coupled to the second predriver.

5. The integrated circuit of claim 4 , wherein the first predriver controls a slew rate of the gate terminal of the PMOS transistor based on the level shifted data.

6. The integrated circuit of claim 5 , wherein the second predriver controls a slew rate of the gate terminal of the NMOS transistor based on the level shifted complimentary data.

7. An integrated circuit, comprising:
an output pad;
an I/O driver coupled to the output pad;
a maximum voltage generator that receives a core supply voltage and an I/O supply voltage and outputs a maximum voltage corresponding to a higher of the core supply voltage and the I/O supply voltage;
a core that provides a data value; and a predriver block that receives the data value and the maximum voltage and controls the I/O driver to drive the data value at the output pad, wherein the maximum voltage generator includes:
a first transistor that receives the I/O supply voltage on a source terminal and receives the core supply voltage on a gate terminal;
a second transistor that receives the core supply voltage on a source terminal and receives the I/O supply voltage on a gate terminal;
an output coupled to a drain terminal of the first transistor; and
a third transistor having a source terminal coupled to the output, a gate terminal coupled to the output, and a drain terminal that receives the I/O supply voltage.

8. The integrated circuit of claim 7 , wherein:
the predriver block includes a first level shifter that receives the maximum voltage and the data and shifts the data value to a level of the maximum voltage; and
the predriver block includes a first predriver coupled to the first level shifter, wherein the first predriver receives the level shifted data from the first level shifter and receives the maximum voltage and controls the I/O driver based on the level shifted data.

9. The integrated circuit of claim 8 , wherein the predriver block includes a second level shifter that receives the maximum voltage and complimentary data from the core and shifts the complimentary data to a level of the maximum voltage, wherein the complimentary data is a logical compliment of the data.

10. The integrated circuit of claim 9 , wherein the predriver block includes a second predriver coupled to the second level shifter, wherein the second predriver receives the level shifted complimentary data from the second level shifter and receives the maximum voltage and controls the I/O driver based on the complimentary level shifted data.

11. A method, comprising:
receiving, with a maximum voltage generator of an integrated circuit, a first supply voltage and a second supply voltage; comparing, with the maximum voltage generator, the first supply voltage to the second supply voltage;
outputting, with the maximum voltage generator, a maximum voltage corresponding to a higher of the first supply voltage and the second supply voltage based on the comparison;
receiving the maximum voltage with a predriver block of the integrated circuit;
powering, with the first supply voltage, a core of the integrated circuit including a plurality of transistors;
receiving, with a first level shifter of the predriver block, data from the core and the maximum voltage;
shifting, with the first level shifter, the data to a level of the maximum voltage;
receiving, with a first predriver of the predriver block, the level shifted data and the maximum voltage; and
controlling, with the predriver block, an I/O driver of the integrated circuit to output the level shifted data on an output pad of the integrate circuit.

12. The method of claim 11 , further comprising controlling, with the predriver, a gate terminal of a transistor of the I/O driver based on the level shifted data.

13. The method of claim 11 , wherein the predriver block includes a second level shifter that receives the maximum voltage and complimentary data from the core and shifts the complimentary data to a level of the maximum voltage, wherein the complimentary data is a logical compliment of the data.

14. The method of claim 13 , wherein the predriver block includes a second predriver coupled to the second level shifter, wherein the second predriver receives the level shifted complimentary data from the second level shifter and receives the maximum voltage and controls the I/O driver based on the complimentary level shifted data.

15. The method of claim 14 , wherein the I/O driver includes:
a PMOS transistor having a source terminal coupled the I/O supply voltage, a drain terminal coupled to the output pad, and a gate terminal coupled to the first predriver; and
an NMOS transistor having a source terminal coupled to ground, a drain terminal coupled to the output pad, and a gate terminal coupled to the second predriver.

16. The method of claim 15 , wherein the first predriver controls a slew rate of the gate terminal of the PMOS transistor based on the level shifted data.

17. The method of claim 16 , wherein the second predriver controls a slew rate of the gate terminal of the NMOS transistor based on the level shifted complimentary data.

18. The method of claim 11 , wherein the first supply voltage is a core supply voltage and the second supply voltage is an I/O suppl

Assignees

• St Microelectronics Int Nv

Inventors

• Kumar Kailash
• Kumar Ravinder

Classifications

• H03K19/00384 Primary

  in field effect transistor circuits · CPC title

• H03K19/018521 Primary

  of complementary type, e.g. CMOS · CPC title