RC-IGBT with lifetime control layer

Patent metadata

Field	Value
Publication number	US-12159944-B2
Application number	US-202117168750-A
Country	US
Kind code	B2
Filing date	Feb 5, 2021
Priority date	May 27, 2020
Publication date	Dec 3, 2024
Grant date	Dec 3, 2024

Abstract

A semiconductor device includes a transistor and a diode formed at a common semiconductor substrate. The diode region includes: a fifth semiconductor layer of a second conductivity type; a second semiconductor layer of the second conductivity type provided on the fifth semiconductor layer; a third semiconductor layer of a first conductivity type provided closer to a first main surface of the semiconductor substrate; a sixth semiconductor layer of the first conductivity type provided on the third semiconductor layer; and a lifetime control layer formed of a crystal defect layer reaching a deeper position than an intermediate position of the second semiconductor layer between an end of the third semiconductor layer in a thickness direction as viewed from the first main surface and an end of the fifth semiconductor layer in a thickness direction as viewed from a second main surface.

First claim

What is claimed is:

1. A semiconductor device comprising a transistor and a diode formed at a common semiconductor substrate,
the semiconductor substrate including:
a transistor region in which the transistor is formed; and
a diode region in which the diode is formed,

the transistor region including:
a first semiconductor layer of a first conductivity type provided on a side of a second main surface of the semiconductor substrate;
a second semiconductor layer of a second conductivity type provided on the first semiconductor layer;
a third semiconductor layer of the first conductivity type provided closer to a first main surface of the semiconductor substrate than is the second semiconductor layer;
a fourth semiconductor layer of the second conductivity type provided on the third semiconductor layer;
a second electrode electrically connected to the fourth semiconductor layer; and
a first electrode electrically connected to the first semiconductor layer, the diode region including:
a fifth semiconductor layer of the second conductivity type provided on the side of the second main surface of the semiconductor substrate;
the second semiconductor layer provided on the fifth semiconductor layer;
the third semiconductor layer provided closer to the first main surface of the semiconductor substrate than is the second semiconductor layer;
a sixth semiconductor layer of the first conductivity type provided on the third semiconductor layer;
the second electrode electrically connected to the sixth semiconductor layer;
the first electrode electrically connected to the fifth semiconductor layer; and
a lifetime control layer formed of a crystal defect layer reaching a deeper position than an intermediate position of the second semiconductor layer equidistant between an end of the third semiconductor layer in a thickness direction as viewed from the first main surface and an end of the fifth semiconductor layer in a thickness direction as viewed from the second main surface, wherein

in the lifetime control layer, a crystal defect density maximum depth is set at a deeper position than the intermediate position, the crystal defect density maximum depth being a depth at which a peak is formed in the density of crystal defect,
the lifetime control layer includes a projecting part projecting from the diode region into only a part of the of the whole of the transistor region and directly under the fourth semiconductor layer across a boundary between the diode region and the transistor region, and
with a thickness from the end of the third semiconductor layer in the thickness direction to the intermediate position defined as t1 and a thickness from the intermediate position to the crystal defect density maximum depth defined as t2, the projecting part has a projecting width w in a plane direction projecting from the boundary set to fulfill the following: w>((3×t1)−t2)/2.

2. The semiconductor device according to claim 1 , wherein
the lifetime control layer is set a depth greater than the intermediate position and not reaching the fifth semiconductor layer.

3. A semiconductor device comprising a transistor and a diode formed at a common semiconductor substrate,
the semiconductor substrate including:
a transistor region in which the transistor is formed; and
a diode region in which the diode is formed,
the transistor region including:
a first semiconductor layer of a first conductivity type provided on a side of a second main surface of the semiconductor substrate;
a second semiconductor layer of a second conductivity type provided on the first semiconductor layer;
a third semiconductor layer of the first conductivity type provided closer to a first main surface of the semiconductor substrate than is the second semiconductor layer;
a fourth semiconductor layer of the second conductivity type provided on the third semiconductor layer;
a second electrode electrically connected to the fourth semiconductor layer; and
a first electrode electrically connected to the first semiconductor layer,

the diode region including:
a fifth semiconductor layer of the second conductivity type provided on the side of the second main surface of the semiconductor substrate;
the second semiconductor layer provided on the fifth semiconductor layer;
the third semiconductor layer provided closer to the first main surface of the semiconductor substrate than is the second semiconductor layer;
a sixth semiconductor layer of the first conductivity type provided on the third semiconductor layer;
the second electrode electrically connected to the sixth semiconductor layer;
the first electrode electrically connected to the fifth semiconductor layer; and
a lifetime control layer formed of a crystal defect layer reaching a deeper position than an intermediate position of the second semiconductor layer equidistant between an end of the third semiconductor layer in a thickness direction as viewed from the first main surface and an end of the fifth semiconductor layer in a thickness direction as viewed from the second main surface, wherein

in the lifetime control layer, a crystal defect density maximum depth is set at a deeper position than the intermediate position, the crystal defect density maximum depth being a depth at which a peak is formed in the density of crystal defect,
the semiconductor substrate includes a terminal region provided around a region in which at least the diode region and the transistor region are provided,
the lifetime control layer includes a projecting part projecting from the diode region into a part of the terminal region across a boundary between the diode region and the terminal region, and
with a thickness from the end of the third semiconductor layer in the thickness direction to the intermediate position defined as t1 and a thickness from the intermediate position to the crystal defect density maximum depth defined as t2, the projecting part has a projecting width w in a plane direction projecting from the boundary set to fulfill the following: w>((3×t1)−12)/2.

Assignees

• Mitsubishi Electric Corp

Inventors

• Soneda Shinya
• Harada Kenji
• Otsuka Kakeru

Classifications

• H10D84/811 Primary

  Combinations of field-effect devices and one or more diodes, capacitors or resistors · CPC title

• H10D12/481

  having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs · CPC title

• H10D84/204

  of combinations of diodes or capacitors or resistors · CPC title

• H10D62/405

  Orientations of crystalline planes · CPC title

• H10D8/422

  PN diodes having the PN junctions in mesas · CPC title