Scalable and interoperable PHYLESS die-to-die IO solution

Patent metadata

Field	Value
Publication number	US-12159840-B2
Application number	US-202016910023-A
Country	US
Kind code	B2
Filing date	Jun 23, 2020
Priority date	Jun 23, 2020
Publication date	Dec 3, 2024
Grant date	Dec 3, 2024

Abstract

Embodiments disclosed herein include multi-die packages with interconnects between the dies. In an embodiment, an electronic package comprises a package substrate, and a first die over the package substrate. In an embodiment, the first die comprises a first IO bump map, where bumps of the first IO bump map have a first pitch. In an embodiment, the electronic package further comprises a second die over the package substrate. In an embodiment, the second die comprises a second IO bump map, where bumps of the second IO bump map have a second pitch that is different than the first pitch. In an embodiment, the electronic package further comprises interconnects between the first IO bump map and the second IO bump map.

First claim

What is claimed is:

1. An electronic package, comprising:
a package substrate;
a first die over the package substrate, wherein the first die comprises a first IO bump map, wherein bumps of the first IO bump map have a first pitch;
a second die over the package substrate, wherein the second die comprises a second IO bump map, wherein bumps of the second IO bump map have a second pitch that is different than the first pitch;
interconnects between the first IO bump map and the second IO bump map, wherein the interconnects communicatively couple the first IO bump map to the second IO bump map; and
a bridge die embedded in the package substrate, wherein the interconnects are on the bridge die, the bridge die comprising a first metal layer above a second metal layer, wherein both the first metal layer and the second layer are coupled to the interconnects to communicatively couple the first IO bump map to the second IO bump map, wherein the first metal layer couples an outermost interconnect of the first die to a second outermost interconnect of the second die, and wherein the second metal layer couples an outermost interconnect of the second die to a second outermost interconnect of the first die.

2. The electronic package of claim 1 , wherein the first bump map has a first width along an edge of the first die, and wherein the second bump map has a second width along an edge of the second die, wherein the first width matches the second width.

3. The electronic package of claim 1 , wherein the first bump map has a first depth into the first die, and wherein the second bump map has a second depth into the second die, wherein the first depth is different than the second depth.

4. The electronic package of claim 1 , wherein the interconnects are within the package substrate.

5. The electronic package of claim 1 , wherein the first pitch is approximately 55 μm or larger, and wherein the second pitch is approximately 55 μm or smaller.

6. The electronic package of claim 1 , wherein the second pitch is approximately 45 μm, approximately 36 μm, or approximately 25 μm.

7. The electronic package of claim 1 , wherein the first bump map has a first number of signal bumps, and wherein the second bump map has a second number of signal bumps, wherein the first number of signal bumps is equal to the second number of signal bumps.

8. The electronic package of claim 7 , wherein the first number of signal bumps is sixty.

9. The electronic package of claim 1 , wherein the first bump map comprises:
a first transmitter region; and
a first receiver region, wherein the first transmitter region is along an edge of the first die; and
wherein the second bump map comprises:
a second transmitter region; and
a second receiver region, wherein the second transmitter region is along an edge of the second die.

10. An electronic package, comprising:
a package substrate with a plurality of metal layers embedded in the package substrate, wherein a first metal layer, a third metal layer, and a fifth metal layer are power and/or ground layers, and wherein a second metal layer and a fourth metal layer are signaling layers;
a first die over the package substrate, wherein the first die comprises:
a first bump map with a first transmitter region and a first receiver region;

a second die over the package substrate, wherein the second die comprises:
a second bump map with a second transmitter region and a second receiver region; and

wherein the first transmitter region is electrically coupled to the second receiver region by channels in the second metal layer, and wherein the second transmitter region is electrically coupled to the first receiver region by channels in the fourth metal layer.

11. The electronic package of claim 10 , wherein a set of power pads and a set of ground pads are depopulated from the second metal layer.

12. The electronic package of claim 11 , wherein the depopulated set of power pads and the depopulated ground pads comprise all of the power pads and all of the ground pads below the second transmitter region.

13. The electronic package of claim 11 , wherein none of the power pads and none of the ground pads are depopulated from the fourth metal layer.

14. The electronic package of claim 10 , wherein an edge of the first bump map is offset from an edge of the second bump map.

15. The electronic package of claim 14 , wherein the first bump map has a first width along an edge of the first die, and wherein the second bump map has a second width along an edge of the second die, wherein the first width is equal to the second width.

16. The electronic package of claim 10 , wherein the channels in the second metal layer and the channels in the fourth metal layer have the same length.

17. A semiconductor die, comprising:
a semiconductor substrate, wherein the semiconductor substrate comprises:
an IO transmitter region comprising a plurality of transmitter circuits; and
an IO receiver region comprising a plurality of receiver circuits;

a plurality of metal layers over the semiconductor substrate;
a plurality of first bumps over the IO transmitter region, wherein individual transmitter circuits are aligned with individual first bumps; and
a plurality of second bumps over the IO receiver region, wherein individual receiver circuits are not aligned with individual second bumps.

18. The semiconductor die of claim 17 , wherein individual first bumps are electrically coupled to individual transmitter circuits by vertical interconnects through the plurality of metal layers, and wherein individual second bumps are electrically coupled to the individual receiver circuits by vertical interconnects and a horizontal leadway segment in the plurality of metal layers.

19. The semiconductor die of claim 18 , wherein the horizontal leadway segment has a length that is approximately 200 μm or greater.

20. The semiconductor die of claim 18 , wherein the horizontal leadway adds approximately 65 Ohm to the electrical channel between the second bumps and the receiver circuit.

21. The semiconductor die of claim 17 , wherein the plurality of receiver circuits are arranged in an array within the IO receiver region.

22. An electronic system, comprising:
a board;
a package substrate coupled to the board;
a first die over the package substrate, wherein the first die comprises a first IO bump map, wherein bumps of the first IO bump map have a first pitch;
a second die over the package substrate, wherein the second die comprises a second IO bump map, wherein bumps of the second IO bump map have a second pitch that is different than the first pitch;
interconnects between the first IO bump map and the second IO bump map, wherein the interconnects communicatively couple the first IO bump map to the second IO bump map; and
a bridge die embedded in the package substrate, wherein the interconnects are on the bridge die, the bridge die comprising a first metal layer above a second metal layer, wherein both the first metal layer and the second layer are coupled to the interconnects to communicatively couple the first IO bump map to the second IO bump map, wherein the first metal layer couples an outermost interconnect of the first die to a second outermost interconnect of the second die, and wherein the second metal layer couples an outermost interconnect of the second die to a second outermost interconnect of the first die.

23. The electronic system of claim 22 , wherein the first bump map has

Assignees

• Intel Corp

Inventors

• Qian Zhiguo
• Pasdast Gerald
• Zeng Juan
• Wang Peipei
• Siddiqui Ahmad
• Seshan Lakshmipriya

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W70/611

  for connecting multiple chips together · CPC title

• H10W70/618

  the bridge chips being embedded in the package substrates, interposers or redistribution layers · CPC title

• H10W72/248

  Top-view layouts, e.g. mirror arrays · CPC title

• H10W72/242

  relative to the surface, e.g. recessed, protruding · CPC title