Info packages including thermal dissipation blocks

Patent metadata

Field	Value
Publication number	US-12159791-B2
Application number	US-202318357520-A
Country	US
Kind code	B2
Filing date	Jul 24, 2023
Priority date	May 13, 2021
Publication date	Dec 3, 2024
Grant date	Dec 3, 2024

Abstract

A method includes forming a package, which includes forming a plurality of redistribution lines over a carrier, and forming a thermal dissipation block over the carrier. The plurality of redistribution lines and the thermal dissipation block are formed by common processes. The thermal dissipation block has a first metal density, and the plurality of redistribution lines have a second metal density smaller than the first metal density. The method further includes forming a metal post over the carrier, placing a device die directly over the thermal dissipation block, and encapsulating the device die and the metal post in an encapsulant. The package is then de-bonded from the carrier.

First claim

What is claimed is:

1. A package comprising:
a device die;
a plurality of redistribution lines overlying the device die, wherein the plurality of redistribution lines are electrically connected to the device die;
a metallic block overlapped by the device die, wherein in a top view of the package, the metallic block comprises a straight edge extending substantially from a first edge to a second edge of the device die, and wherein the first edge and the second edge are first opposing edges of the device die; and
an encapsulant encapsulating the device die therein.

2. The package of claim 1 , wherein in the top view of the package, the metallic block further comprises an additional straight edge extending substantially from a third edge to a fourth edge of the device die, and wherein the third edge and the fourth edge are perpendicular to the first edge and the second edge.

3. The package of claim 1 , wherein in the top view of the package, the metallic block comprises a first plurality of strips parallel to each other.

4. The package of claim 3 , wherein the first plurality of strips are physically separated from each other, and the package further comprises a second plurality of strips parallel to each other, wherein the second plurality of strips are underlying the first plurality of strips, and wherein in the top view, the second plurality of strips are perpendicular to the first plurality of strips.

5. The package of claim 3 , wherein the first plurality of strips are physically separated from each other, and the package further comprises a second plurality of strips parallel to each other, and wherein the second plurality of strips are overlapped by the first plurality of strips.

6. The package of claim 3 further comprising a second plurality of strips parallel to each other, wherein the second plurality of strips are joined with the first plurality of strips to form a mesh.

7. The package of claim 1 further comprising a plurality of thermal dissipation features overlapping the device die and distributed in a plurality of layers, wherein the plurality of thermal dissipation features in the plurality of layers are physically joined as an integrated feature.

8. The package of claim 7 further comprising:
a first Under-Bump Metallurgy (UBM) over and electrically connecting to one of the plurality of redistribution lines;
a first solder region over and contacting the first UBM;
a second UBM over and joined to a top one of the plurality of thermal dissipation features; and
an underfill over and contacting an entirety of the second UBM.

9. The package of claim 1 further comprising a solder region joined with the metallic block.

10. The package of claim 9 , wherein the solder region is a dummy feature.

11. A package comprising:
a first package component comprising:
a plurality of dielectric layers;
a plurality of redistribution lines in the plurality of dielectric layers;
a thermal dissipation block in the plurality of dielectric layers and comprising:
a first plurality of portions in a first layer of the plurality of dielectric layers;
a second plurality of portions in a second layer of the plurality of dielectric layers; and
a plurality of vias joining the first plurality of portions to the second plurality of portions, and electrically interconnecting the first plurality of portions and the second plurality of portions as an integrated block;

a device die overlapping the thermal dissipation block, wherein the plurality of redistribution lines are located in regions that are on opposing sides of the thermal dissipation block; and

a second package component bonding to the first package component, wherein the second package component is electrically connected to the device die.

12. The package of claim 11 , wherein the first package component is free from redistribution lines that are inside the thermal dissipation block and are also configured for conducting signals.

13. The package of claim 11 , wherein the thermal dissipation block comprises a plurality of meshes at different layers, with the first plurality of portions and the second plurality of portions being parts of the plurality of meshes, and wherein the plurality of redistribution lines are located in the regions that are on the opposing sides of the meshes.

14. The package of claim 13 further comprising dielectric materials filled in the plurality of meshes.

15. The package of claim 11 , wherein the thermal dissipation block is electrically grounded.

16. The package of claim 11 , wherein the plurality of redistribution lines are in the regions surrounding the thermal dissipation block, wherein the plurality of redistribution lines have a first metal density, and the thermal dissipation block has a second metal density greater than about two times the first metal density.

17. A package comprising:
a plurality of dielectric layers;
a plurality of redistribution lines in the plurality of dielectric layers;
a first thermal dissipation block in the plurality of dielectric layers, wherein the first thermal dissipation block has a first metal density, and the plurality of redistribution lines have a second metal density smaller than the first metal density;
a device die overlapping the first thermal dissipation block; and
an encapsulant encapsulating the device die.

18. The package of claim 17 , wherein in a top view of the device die and the first thermal dissipation block, substantially an entirety of the first thermal dissipation block is overlapped by the device die.

19. The package of claim 17 further comprising a second thermal dissipation block overlapping the device die.

20. The package of claim 19 , wherein some of the plurality of redistribution lines penetrate through, and are electrically decoupled from, the second thermal dissipation block.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Ching-Yi
• Chen Yu-Hao
• Chang Fong-Yuan
• Huang Po-Hsiang
• Lee Jyh Chwen Frank
• Chen Shuo-Mao

Classifications

• H10W90/722

  between stacked chips · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title

• H10W70/099

  Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers · CPC title

• H10W72/073

  of die-attach connectors · CPC title