Method for manufacturing a composite structure comprising a thin layer made of monocrystalline sic on a carrier substrate made of SiC

Patent metadata

Field	Value
Publication number	US-12159781-B2
Application number	US-202117907517-A
Country	US
Kind code	B2
Filing date	Jan 12, 2021
Priority date	Mar 27, 2020
Publication date	Dec 3, 2024
Grant date	Dec 3, 2024

Abstract

A method for manufacturing a composite structure comprising a thin layer made of monocrystalline silicon carbide arranged on a carrier substrate made of silicon carbide, the method comprising: a) a step of providing a donor substrate made of monocrystalline silicon carbide, b) a step of ion implantation of light species into the donor substrate, to form a buried brittle plane delimiting the thin layer between the buried brittle plane and a free surface of the donor substrate, c) a succession of n steps of forming crystalline carrier layers, with n greater than or equal to 2; the n crystalline carrier layers being positioned on the front face of the donor substrate successively one on the other, and forming the carrier substrate; each formation step comprising: direct liquid injection chemical vapor deposition, at a temperature below 900° C., to form a carrier layer, the carrier layer being formed by an at least partially amorphous SiC matrix, and having a thickness of less than or equal to 200 microns; a crystallization heat treatment of the carrier layer, at a temperature of less than or equal to 1000° C., to form a crystalline carrier layer; d) a step of separation along the buried brittle plane, to form, on the one hand, a composite structure comprising the thin layer on the carrier substrate and, on the other hand, the rest of the donor substrate.

First claim

The invention claimed is:

1. A process for manufacturing a composite structure comprising a thin layer made of monocrystalline silicon carbide arranged on a carrier substrate made of silicon carbide, the process comprising:
a) a step of providing a donor substrate made of monocrystalline silicon carbide;
b) a step of ion implantation of light species into the donor substrate to form a buried brittle plane delimiting the thin layer between the buried brittle plane and a free surface of the donor substrate;
c) a succession of n steps of forming crystalline carrier layers, with n greater than or equal to 2, the n crystalline carrier layers being positioned on a front face of the donor substrate successively one on the other and forming the carrier substrate, each formation step comprising:
direct liquid injection chemical vapor deposition, at a temperature below 900° C., to form a carrier layer, the carrier layer being formed by an at least partially amorphous SiC matrix, and having a thickness of less than or equal to 200 microns; and
a crystallization heat treatment of the carrier layer, at a temperature of less than or equal to 1000° C., to form a crystalline carrier layer; and

d) a step of separation along the buried brittle plane to form, on the one hand, a composite structure comprising the thin layer on the carrier substrate and, on the other hand, a remainder of the donor substrate.

2. The process of claim 1 , further comprising:
e) a step of mechanical and/or chemical treatment of the composite structure, the mechanical and/or chemical treatment being applied to a free rear face of the composite structure, and/or to a free face of the thin layer.

3. The process of claim 2 , wherein step e) comprises simultaneous chemical-mechanical polishing of the front face and of the rear face of the composite structure.

4. The process of claim 1 , wherein chemical etching, mechanical grinding and/or chemical-mechanical polishing is applied to a free face of the carrier substrate between step c) and step d).

5. The process of claim 1 , wherein the thickness of each deposited carrier layer is less than or equal to 100 microns.

6. The process of claim 1 , wherein the chemical vapor depositions in step c) are performed at a temperature of between 100° C. and 800° C.

7. The process of claim 1 , wherein the chemical vapor depositions in step c) are performed at a pressure of between 1 Torr and 500 Torr.

8. The process of claim 1 , wherein precursors used during the chemical vapor depositions in step c) are chosen from polysilylethylene and disilabutane.

9. The process of claim 1 , wherein step c) comprises a succession of n steps of forming crystalline carrier layers, with n between 3 and a few dozen.

10. The process of claim 1 , wherein step a) comprises:
a′) a step of providing an initial substrate made of monocrystalline silicon carbide; and
a″) a step of epitaxial growth of a monocrystalline silicon carbide donor layer on the initial substrate to form the donor substrate, the monocrystalline silicon carbide donor layer having a density of crystal defects less than that of the initial substrate.

11. The process of claim 10 , wherein step a′) comprises formation, on the initial substrate, of a monocrystalline conversion layer to convert basal plane dislocation defects of the initial substrate into threading edge dislocation defects.

12. The process of claim 10 , wherein the epitaxial growth step a″) is performed at a temperature above 1200° C.

13. The process of claim 1 , wherein the separation step d) is performed at a temperature greater than or equal to the temperature of the crystallization heat treatments of step c).

14. The process of claim 1 , further comprising a step of reconditioning the remainder of the donor substrate to reuse the donor substrate as another initial substrate or as another donor substrate.

15. The process of claim 5 , wherein the thickness of each deposited carrier layer is less than or equal 50 microns.

16. The process of claim 15 , wherein the thickness of each deposited carrier layer is less than or equal 10 microns.

17. The process of claim 6 , wherein the chemical vapor depositions in step c) are performed at a temperature of between 200°° C. and 600° C.

18. The process of claim 12 , wherein the epitaxial growth step a″) is performed at a temperature between 1500° C. and 1650° C.

Assignees

• Soitec Silicon On Insulator

Inventors

• Biard Hugo

Classifications

• H10P70/40

  Cleaning for reclaiming · CPC title

• H10P90/1904

  Preparing vertically inhomogeneous wafers · CPC title

• H10P90/00 Primary

  Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement · CPC title

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P14/24

  using chemical vapour deposition [CVD] · CPC title