Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells

Patent metadata

Field	Value
Publication number	US-12159674-B2
Application number	US-202117409476-A
Country	US
Kind code	B2
Filing date	Aug 23, 2021
Priority date	Aug 23, 2021
Publication date	Dec 3, 2024
Grant date	Dec 3, 2024

Abstract

A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. Laterally-spaced memory-block regions are formed that individually comprise a vertical stack comprising alternating first tiers and second tiers are formed directly above the conductor tier. Material of the first tiers is sacrificial and of different composition from material of the first tiers. Channel-material strings extend through the first tiers and the second tiers. Conducting material in a lowest of the first tiers is formed that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. A horizontally-elongated trench is formed between immediately-laterally-adjacent of the memory-block regions. The trenches extend downwardly into the conducting material. After forming the trenches, lateral-sidewall regions of the conducting material that are aside the individual trenches in the lowest first tier is doped with an impurity. The sacrificial material is etched from the first tiers through the trenches selectively relative to the doped lateral-sidewall regions of the conducting material. Other embodiments, including structure, are disclosed.

First claim

The invention claimed is:

1. A method used in forming a memory array comprising strings of memory cells, comprising:
forming a conductor tier comprising conductor material on a substrate;
forming laterally-spaced memory-block regions individually comprising a vertical stack comprising alternating first tiers and second tiers directly above the conductor tier, material of the first tiers being sacrificial and of different composition from material of the first tiers, channel-material strings extending through the first tiers and the second tiers;
forming conducting material in a lowest of the first tiers that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier;
forming horizontally-elongated trenches that are individually between immediately-laterally-adjacent of the memory-block regions and extend downwardly into the conducting material;
after forming the trenches, doping lateral-sidewall regions of the conducting material that are aside the individual trenches in the lowest first tier with an impurity; and
etching the sacrificial material from the first tiers through the trenches with an etching chemistry that physically contacts the sacrificial material and the doped lateral-sidewall regions of the conducting material, the etching of the sacrificial material being done selectively relative to the doped lateral-sidewall regions of the conducting material.

2. The method of claim 1 wherein the conducting material comprises floors in the lowest first tier that are individually directly under the individual trenches, and further comprising doping the floors of the conducting material with the impurity to form impurity-doped floor regions.

3. The method of claim 2 wherein said doping the lateral-sidewall regions and said doping the floors occur at the same time.

4. The method of claim 2 wherein two immediately-adjacent of the doped lateral-sidewall regions and the impurity-doped floor region laterally therebetween collectively join to comprise a generally U-shape in a vertical cross-section in the lowest first tier.

5. The method of claim 4 wherein the lowest first tier has a top, the U of the generally U-shape having a top that is below the top of the lowest first tier.

6. The method of claim 4 wherein the lowest first tier has a top, the U of the generally U-shape having a top that is elevationally-coincident with the top of the lowest first tier.

7. The method of claim 1 wherein the trenches extend downwardly through all of the conducting material to the conductor material of the conductor tier.

8. The method of claim 7 wherein the trenches extend into the conductor material of the conductor tier.

9. A method used in forming a memory array comprising strings of memory cells, comprising: forming a conductor tier comprising conductor material on a substrate: forming laterally-spaced memory-block regions individually comprising a vertical stack comprising alternating first tiers and second tiers directly above the conductor tier, material of the first tiers being sacrificial and of different composition from material of the first tiers, channel-material strings extending through the first tiers and the second tiers; forming conducting material in a lowest of the first tiers that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier; forming horizontally-elongated trenches that are individually between immediately-laterally-adjacent of the memory-block regions and extend downwardly into the conducting material: after forming the trenches, doping lateral-sidewall regions of the conducting material that are aside the individual trenches in the lowest first tier with an impurity; etching the sacrificial material from the first tiers through the trenches selectively relative to the doped lateral-sidewall regions of the conducting material: the trenches extend downwardly through all of the conducting material to the conductor material of the conductor tier; the trenches extend into the conductor material of the conductor tier; and the conductor material comprises conductively-doped semiconductive material directly above and directly against metal material, the trenches extending into the conductively-doped semiconductive material and not to the metal material.

10. The method of claim 1 wherein total impurity concentration in the lateral-sidewall regions is 0.05 to 30.0 atomic percent.

11. The method of claim 10 wherein total impurity concentration in the lateral-sidewall regions is 0.5 to 10.0 atomic percent.

12. The method of claim 1 wherein the impurity is at least one of B, C, N, Ga, and metal material.

13. The method of claim 12 wherein total impurity concentration in the lateral-sidewall regions is 0.05 to 30.0 atomic percent.

14. The method of claim 12 wherein the conducting material comprises conductively-phosphorus-doped silicon.

15. The method of claim 1 wherein the doping comprises gas phase diffusion.

16. The method of claim 1 wherein the doping comprises plasma enhanced doping.

17. The method of claim 1 wherein the doping comprises ion implantation followed by anneal.

18. The method of claim 1 wherein the conducting material comprises conductively-phosphorus-doped silicon and the impurity comprises B.

19. A method used in forming a memory array comprising strings of memory cells, comprising:
forming a conductor tier comprising conductor material on a substrate;
forming a lower portion of a stack that will comprise vertically-alternating first tiers and second tiers above the conductor tier, the stack comprising laterally-spaced memory-block regions, a lowest of the first tiers comprising first sacrificial material;
forming the vertically-alternating first tiers and second tiers of an upper portion of the stack above the lower portion, and forming channel-material strings that extend through the upper portion to the lower portion, material of the first tiers in the upper portion comprising second sacrificial material that is of different composition from material of the first tiers;
forming horizontally-elongated trenches into the stack that are individually laterally-between immediately-laterally-adjacent of the memory-block regions, the trenches extending through the upper portion to the lowest first tier and exposing the first sacrificial material therein;
isotropically etching the exposed first sacrificial material from the lowest first tier through the trenches;
after the isotropically etching, forming conducting material in the lowest first tier that directly electrically couples together the channel material of the channel-material strings and the conductor material of the conductor tier;
after forming the trenches, doping lateral-sidewall regions of the conducting material that are aside the individual trenches in the lowest first tier with an impurity; and
etching the second sacrificial material from the first tiers in the upper portion through the trenches selectively relative to the doped lateral-sidewall regions of the conducting material in the lower portion.

20. The method of claim 19 wherein the conducting material comprises floors in the lowest first tier that are individually directly under the individual trenches, and further comprising doping the floors of the conducting material with the impurity to form impurity-doped floor regions.

21. The method of claim

Assignees

• Micron Technology Inc

Inventors

• Greenlee Jordan D
• Hopkins John D
• Barclay M Jared
• Li Andrew
• Christensen Aireus

Classifications

• H10B43/35

  with cell select transistors, e.g. NAND · CPC title

• H10B43/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/10

  characterised by the top-view layout · CPC title

• H10B41/35

  with a cell select transistor, e.g. NAND · CPC title

• H10B41/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title