Method of fabricating a flip-chip package core substrate with build-up layers

Patent metadata

Field	Value
Publication number	US-12154866-B2
Application number	US-202217891184-A
Country	US
Kind code	B2
Filing date	Aug 19, 2022
Priority date	May 10, 2018
Publication date	Nov 26, 2024
Grant date	Nov 26, 2024

Abstract

A flip-chip packaging substrate and a method for fabricating the same are disclosed. The method includes stacking a plurality of insulating layers having conductive posts in a manner that the conductive posts are stacked on and in contact with one another. The insulating layers and the conductive posts serve as a core layer structure of the flip-chip packaging substrate. As such, the conductive posts having small-sized end surfaces can be fabricated according to the practical need. Therefore, when the thickness of the core layer structure is increased, the present disclosure not only increases the rigidity of the flip-chip packaging substrate so as to avoid warping, but also ensures the design flexibility of the small-sized end surfaces of the conductive posts, allowing high-density electrical connection points and fine-pitch and high-density circuit layers to be fabricated on the core layer structure.

First claim

What is claimed is:

1. A method for fabricating a flip-chip packaging substrate, comprising:
providing an insulating portion having opposite first and second sides;
forming a plurality of first openings from on the first side of the insulating portion toward the second side of the insulating portion;
forming from on the second side of the insulating portion toward the first side of the insulating portion a plurality of second openings corresponding in position to the first openings, wherein corresponding ones of the first and second openings communicate with each other;
forming first conductive posts in the first openings, and forming second conductive posts in the second openings, in a manner that the first conductive posts and the second conductive posts are stacked on and in contact with one another, wherein the second conductive posts and the first conductive posts serve as conductive portions, and the insulating portion and the conductive portions serve as a core layer structure having opposite first and second surfaces, wherein end surfaces of the first conductive posts and the second conductive posts have different sizes; and
forming a circuit portion of a build-up type on the first and second surfaces of the core layer structure at the same or different times with the circuit portion electrically connected to the conductive portions,
wherein two ends of the first conductive posts are free from being formed with pad structures,
wherein two ends of the second conductive posts are free from being formed with pad structures,
wherein the circuit portion includes circuit structures formed on the first and second surfaces of the core layer structure,
wherein the circuit structures include a plurality of dielectric layers and a plurality of circuit layers bonded to the dielectric layers, and
wherein the circuit layers have vertical portions and horizontal portions, the vertical portions of the circuit layers are directly and electrically connected to the first conductive posts and the second conductive posts, and the dielectric layers are spaced between the horizontal portions of the circuit layers and the corresponding first and second surfaces of the core layer structure.

2. The method of claim 1 , wherein the insulating portion of the core layer structure is made of an organic dielectric material free of glass fiber or an inorganic dielectric material free of glass fiber.

Assignees

• Phoenix Pioneer Technology Co Ltd

Inventors

• Chou Pao-Hung
• Yu Chun-Hsien
• Hsu Shih-Ping
• Kuo Tung-Yao

Classifications

• H10W70/655

  Fan-out layouts · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W72/073

  of die-attach connectors · CPC title

• H10W72/30

  Die-attach connectors · CPC title

• H10W72/072

  of bump connectors · CPC title