Display substrate and display apparatus

Patent metadata

Field	Value
Publication number	US-12150353-B2
Application number	US-202117630589-A
Country	US
Kind code	B2
Filing date	Feb 8, 2021
Priority date	Feb 8, 2021
Publication date	Nov 19, 2024
Grant date	Nov 19, 2024

Abstract

A display substrate has sub-pixels. Each column of sub-pixels includes first and second sub-pixels alternately arranged. The display substrate includes a base, a second source-drain metal layer including first and second connection portions, and a first source-drain metal layer including first and second data lines alternately arranged. A pixel driving circuit of each first sub-pixel is connected to a second end of a first connection portion, and a first end there is connected to a corresponding first data line. A pixel driving circuit of each second sub-pixel is connected to a second end of a second connection portion, and a first end thereof is connected to a corresponding second data line. In a same column of sub-pixels, an extension direction of a first line connecting a second end of a first connection portion and a second end of a second connection portion is substantially parallel to a second direction.

First claim

What is claimed is:

1. A display substrate having a plurality of sub-pixels arranged in an array in a first direction and a second direction, each column of sub-pixels including first sub-pixels and second sub-pixels, the first sub-pixels and the second sub-pixels being alternately arranged in the second direction; the display substrate comprising:
a base;
a first source-drain metal layer disposed on the base, the first source-drain metal layer including a plurality of first data lines and a plurality of second data lines, wherein
the first data lines and the second data lines are alternately arranged in the first direction, every two adjacent columns of sub-pixels being provided with a first data line and a second data line therebetween; and
a column of sub-pixels corresponds to a first data line and a second data line that are located at two sides of the column of sub-pixels in the first direction, each first sub-pixel in the column of sub-pixels is electrically connected to the corresponding first data line, and each second sub-pixel in the column of sub-pixels is electrically connected to the corresponding second data line;

a second source-drain metal layer disposed between the base and the first source-drain metal layer, wherein the second source-drain metal layer includes:
a plurality of first connection portions, wherein each first connection portion includes a first end and a second end, a pixel driving circuit of each first sub-pixel is electrically connected to a second end of a first connection portion, and a first end of the first connection portion is electrically connected to a corresponding first data line; and
a plurality of second connection portions, wherein each second connection portion includes a first end and a second end, a pixel driving circuit of each second sub-pixel is electrically connected to a second end of a second connection portion, and a first end of the second connection portion is electrically connected to a corresponding second data line, wherein
in a same column of sub-pixels, an extension direction of a first line connecting a second end of a first connection portion in a first sub-pixel and a second end of a second connection portion in a second sub-pixel is substantially parallel to the second direction, a first end of the first connection portion in the first sub-pixel is located at a first side of the first line, and a first end of the second connection in the second sub-pixel portion is located at a second side of the first line.

2. The display substrate according to claim 1 , further comprising an active layer disposed between the base and the second source-drain metal layer, wherein
the pixel driving circuit of each of the first sub-pixels and the sub-pixels includes a writing transistor, the writing transistor includes an active pattern disposed in the active layer; active patterns of writing transistors in every two adjacent sub-pixels in the first direction have a substantially same distance therebetween, and active patterns of writing transistors of every two adjacent sub-pixels in the second direction have a substantially same distance therebetween; and
in each first sub-pixel, the second end of the first connection portion is electrically connected to an active pattern of a corresponding writing transistor; and in each second sub-pixel, the second end of the second connection portion is electrically connected to an active pattern of a corresponding writing transistor.

3. The display substrate according to claim 2 , wherein first sub-pixels and second sub-pixels in each row are alternately arranged in the first direction; and
in a same row of sub-pixels, an extension direction of a second line connecting a second end of a first connection portion in a first sub-pixel and a second end of a second connection portion in a second sub-pixel is substantially parallel to the first direction, a first end of the first connection portion in the first sub pixel is located at a side of the second line away from an active pattern of a writing transistor in the same first sub-pixel as the first connection portion in the second direction, and a first end of the second connection portion in the second sub-pixel is located at a side of the second line proximate to an active pattern of a writing transistor in the same second sub-pixel as the second connection portion in the second direction.

4. The display substrate according to claim 2 , further comprising a first insulating layer disposed between the second source-drain metal layer and the active layer, the first insulating layer being provided with a plurality of first via holes and a plurality of second via holes therein, wherein
in each first sub-pixel, the second end of the first connection portion is electrically connected to the active pattern of the corresponding writing transistor through a corresponding first via hole, and in each second sub-pixel, the second end of the second connection portion is electrically connected to the active pattern of the corresponding writing transistor through a corresponding second via hole.

5. The display substrate according to claim 4 , wherein the first insulating layer includes a first insulating sub-layer and a second insulating sub-layer, the second insulating sub-layer is disposed between the first insulating sub-layer and the base; and
the display substrate further comprises a second gate metal layer disposed between the first insulating sub-layer and the second insulating sub-layer, the second gate metal layer includes a plurality of first shielding portions and a plurality of second shielding portions, and each sub-pixel is provided with a first shielding portion and a second shielding portion therein, wherein
in each first sub-pixel, an orthogonal projection of the first connection portion on the base overlaps with an orthogonal projection of the second shielding portion on the base, the orthogonal projection of the first connection portion on the base is non-overlapping with an orthogonal projection of the first shielding portion on the base, and an orthogonal projection of the second end of the first connection portion on the base is non-overlapping with the orthogonal projection of the second shielding portion on the base; in each second sub-pixel, an orthogonal projection of the second connection portion on the base overlaps with an orthogonal projection of the first shielding portion on the base, the orthogonal projection of the second connection portion on the base is non-overlapping with an orthogonal projection of the second shielding portion on the base, and an orthogonal projection of the second end of the second connection portion on the base is non-overlapping with the orthogonal projection of the first shielding portion.

6. The display substrate according to claim 5 , wherein in a same row of sub-pixels, first shielding portions and second shielding portions are alternately arranged in the first direction, the first shielding portion and the second shielding portion that are adjacent in the first direction and located in different sub-pixels are formed into a one-piece structure.

7. The display substrate according to claim 1 , wherein a maximum dimension of each first connection portion in an extending direction of the first connection portion is greater than a maximum dimension of each second connection portion in an extending direction of the second connection portion.

8. The display substrate according to claim 1 , wherein an area of the first end of each first connection portion is greater than an area of the second end thereof, and/or an area of the first end of each second connection portion is greater than an area of the second end thereof.

9. The display substrate according to cla

Assignees

• Boe Technology Group Co Ltd

Inventors

• Han Long
• Dong Tian
• Wang Li

Classifications

• G09G2360/16

  Calculation or use of calculated indices related to luminance levels in display data · CPC title

• G09G2320/0233

  Improving the luminance or brightness uniformity across the screen · CPC title

• G09G2310/0202

  Addressing of scan or signal lines · CPC title

• G09G2300/0861

  with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes · CPC title

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title