Integrated assemblies having charge-trapping material arranged in vertically-spaced segments, and methods of forming integrated assemblies

Patent metadata

Field	Value
Publication number	US-12150303-B2
Application number	US-202318138350-A
Country	US
Kind code	B2
Filing date	Apr 24, 2023
Priority date	Apr 3, 2019
Publication date	Nov 19, 2024
Grant date	Nov 19, 2024

Abstract

Some embodiments include a memory array having a vertical stack of alternating insulative levels and wordline levels. The wordline levels have conductive terminal ends within control gate regions. The control gate regions are vertically spaced from one another by first insulative regions which include first insulative material. Charge-storage material is laterally outward of the conductive terminal ends, and is configured as segments. The segments of the charge-storage material are arranged one atop another and are vertically spaced from one another by second insulative regions which include second insulative material. The second insulative material has a different dielectric constant than the first insulative material. Charge-tunneling material extends vertically along the stack, and is adjacent to the segments of the charge-trapping material. Channel material extends vertically along the stack, and is adjacent to the charge-tunneling material. Some embodiments include methods of forming integrated assemblies.

First claim

We claim:

1. An integrated assembly, comprising:
a vertical stack of alternating insulative levels and conductive wordlines; the conductive wordlines having terminal ends and the insulative levels comprising two separate insulative material structures;
a single layer of charge-blocking material extending along the stack;
a charge-storage material comprising discrete segments adjacent the terminal ends of the conductive wordlines;
a charge-tunneling material extending vertically along the stack; and
a channel material extending vertically along the stack.

2. The integrated assembly of claim 1 wherein the discrete segments of the charge-storage material are vertically spaced from the insulative levels by only the single layer of the charge-blocking material.

3. The integrated assembly of claim 1 wherein a vertical dimension of each discrete segment of the charge-storage material approximates a vertical dimension of each conductive wordline.

4. The integrated assembly of claim 1 further comprising a liner of dielectric-barrier material surrounding each conductive wordline.

5. The integrated assembly of claim 1 wherein the conductive wordlines comprise two separate conductive material structures.

6. The integrated assembly of claim 1 wherein one of the two separate insulative material structures comprises a terminal end of each insulative level.

7. The integrated assembly of claim 1 wherein one of the two separate insulative material structures comprises a lower dielectric constant than the other one of the two separate insulative material structures.

8. The integrated assembly of claim 1 wherein one of the two separate insulative material structures comprises a more porous structure than the other one of the two separate insulative material structures.

9. The integrated assembly of claim 1 wherein the charge-storage material comprises at least one of silicon oxynitride, conductive nanodots and floating gate material.

10. The integrated assembly of claim 1 wherein the charge-storage material comprises polycrystalline silicon.

11. A method of forming an integrated assembly, comprising:
forming a vertical stack of alternating insulative levels and sacrificial levels, the sacrificial levels comprising terminal ends configured as first recesses;
forming an insulative material along the vertical stack and filling the first recesses;
removing the insulative material along the sacrificial levels, the removing forming second recesses at terminal ends of the sacrificial levels; and
forming charge-storage material within the second recesses leaving discrete segments adjacent the terminal ends of the sacrificial levels.

12. The method of claim 11 further comprising forming a single liner of charge-blocking material between the charge-storage material and the vertical stack.

13. The method of claim 11 further comprising replacing material in the sacrificial levels with conductive material after the filling of the first recesses.

14. The method of claim 11 further comprising replacing material in the sacrificial levels with conductive material after the forming of the second recesses.

15. The method of claim 11 further comprising replacing material in the sacrificial levels with conductive material after the forming of the charge-storage material.

16. The method of claim 11 further comprising replacing material in the sacrificial levels with two separate structures of conductive material.

17. The method of claim 11 further comprising forming charge-tunneling material along the vertical stack.

18. The method of claim 11 further comprising forming channel material along the vertical stack.

Assignees

• Lodestar Licensing Group Llc

Inventors

• Kim Byeung Chul
• Fabreguette Francois H
• Hill Richard J
• Narayanan Purnima
• Surthi Shyam

Classifications

• H10P14/6927

  the material being a silicon oxynitride, e.g. SiON or SiON:H · CPC title

• H10D64/037

  comprising charge-trapping insulators · CPC title

• H10B43/35

  with cell select transistors, e.g. NAND · CPC title

• G11C16/08 Primary

  Address circuits; Decoders; Word-line control circuits · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title