Solid-state imaging device with transistor drain connected to sense node of logarithmic conversion circuit

Patent metadata

Field	Value
Publication number	US-12149839-B2
Application number	US-202118011437-A
Country	US
Kind code	B2
Filing date	Apr 23, 2021
Priority date	Jun 26, 2020
Publication date	Nov 19, 2024
Grant date	Nov 19, 2024

Abstract

Suppressing a dead period at the time of mode switching. A solid-state imaging device includes: a plurality of pixels ( 300 ) that each outputs a luminance change of incident light; and a detection circuit ( 305 ) that outputs an event signal based on the luminance change output from each of the pixels, in which each of the pixels includes: a photoelectric conversion element ( 311 ) that generates a charge according to an incident light amount; a logarithmic conversion circuit ( 312, 313 ) that is connected to the photoelectric conversion element and converts a photocurrent flowing out of the photoelectric conversion element into a voltage signal corresponding to a logarithmic value of the photocurrent; and a first transistor ( 318 ) having a drain connected to a sense node of the logarithmic conversion circuit.

First claim

The invention claimed is:

1. A solid-state imaging device comprising:
a plurality of pixels that each outputs a luminance change of incident light; and
a detection circuit that outputs an event signal based on the luminance change output from each of the plurality of pixels,
wherein each of the plurality of pixels includes:
a photoelectric conversion element that generates a charge according to an incident light amount;
a logarithmic conversion circuit that is connected to the photoelectric conversion element and converts a photocurrent flowing out of the photoelectric conversion element into a voltage signal corresponding to a logarithmic value of the photocurrent; and
a first transistor having a drain connected to a sense node of the logarithmic conversion circuit.

2. The solid-state imaging device according to claim 1 , wherein the first transistor has a source connected to a first potential that is equal to or higher than a reference potential and lower than a power supply voltage.

3. The solid-state imaging device according to claim 2 ,
wherein each of the plurality of pixels further includes a first circuit that outputs a luminance change of the incident light that has entered on the photoelectric conversion element based on the voltage signal output from the logarithmic conversion circuit, and
the detection circuit includes a second circuit that outputs the event signal based on the luminance change output from each of the plurality of pixels.

4. The solid-state imaging device according to claim 2 , wherein the reference potential is either a negative potential or a ground potential.

5. The solid-state imaging device according to claim 2 , wherein the first potential is a potential lower than a potential of the sense node at normal operation of the logarithmic conversion circuit.

6. The solid-state imaging device according to claim 2 ,
wherein the logarithmic conversion circuit includes:
a second transistor having a gate connected to the photoelectric conversion element; and
a third transistor having a source connected to the photoelectric conversion element,
the third transistor has a gate connected to a drain of the second transistor, and
the sense node is a wiring line connected to the gate of the second transistor.

7. The solid-state imaging device according to claim 6 , wherein each of the plurality of pixels further includes a fourth transistor having a drain connected to the gate of the second transistor and to the source of the third transistor, and having a source connected to the photoelectric conversion element.

8. The solid-state imaging device according to claim 7 ,
wherein each of the plurality of pixels further includes:
a fifth transistor having a source connected to the photoelectric conversion element; and
a readout circuit that is connected to a drain of the fifth transistor and generates a pixel signal according to a charge generated in the photoelectric conversion element.

9. The solid-state imaging device according to claim 8 , wherein the first transistor is connected to the sense node through the fifth transistor and the fourth transistor.

10. The solid-state imaging device according to claim 8 , wherein each of the plurality of pixels further includes a sixth transistor connected to the drain of the fourth transistor and to the drain of the fifth transistor.

11. The solid-state imaging device according to claim 10 , wherein the first transistor is connected to the sense node through the sixth transistor.

12. The solid-state imaging device according to claim 8 ,
wherein the readout circuit includes the first transistor having the source connected to the drain of the fifth transistor and having the drain connected to the first potential.

13. The solid-state imaging device according to claim 12 , wherein each of the plurality of pixels further includes a sixth transistor connected to the drain of the fourth transistor and to the drain of the fifth transistor.

14. The solid-state imaging device according to claim 8 , wherein the first transistor is connected to the sense node through the fourth transistor.

15. The solid-state imaging device according to claim 7 ,
wherein each of the plurality of pixels further includes:
a fifth transistor having a source connected to the drain of the fourth transistor; and
a sixth transistor having a drain connected to the drain of the fourth transistor, to the source of the third transistor, and to the gate of the second transistor, and having a source connected to the drain of the fifth transistor, and
the first transistor is connected to the sense node through the sixth transistor.

16. The solid-state imaging device according to claim 15 ,
wherein each of the plurality of pixels further includes a readout circuit that is connected to the drain of the fifth transistor and generates a pixel signal according to a charge generated in the photoelectric conversion element, and
the readout circuit includes the first transistor having the source connected to the drain of the fifth transistor and having the drain connected to the first potential.

17. The solid-state imaging device according to claim 1 ,
wherein each of the plurality of pixels further includes a fifth transistor having a source connected to the photoelectric conversion element, and
the solid-state imaging device further includes a common line that commonly connects the drain of the fifth transistor among the plurality of pixels.

18. The solid-state imaging device according to claim 17 , further comprising a readout circuit that is connected to the common line and generates a pixel signal according to a charge generated in the photoelectric conversion element of each of the plurality of pixels.

19. The solid-state imaging device according to claim 17 , wherein the first transistor is connected to the common line and shared by the plurality of pixels.

20. The solid-state imaging device according to claim 1 ,
wherein the photoelectric conversion elements included in each of the plurality of pixels are arranged in a matrix on an element formation surface of a semiconductor substrate, and
the first transistor is disposed on the element formation surface between the photoelectric conversion elements arranged in the matrix.

Assignees

• Sony Semiconductor Solutions Corp

Inventors

• Imoto Tsutomu
• Ikeda Yusuke
• Niwa Atsumi
• Suzuki Atsushi
• Etou Shinichirou
• Takamiya Kenichi
• Maruyama Takuya
• Hiyoshi Ren

Classifications

• H04N25/60

  Noise processing, e.g. detecting, correcting, reducing or removing noise · CPC title

• H04N25/78

  Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters · CPC title

• H10F39/811

  Interconnections · CPC title

• H10F39/8037

  the integrated elements comprising a transistor · CPC title

• H10F39/803 Primary

  Pixels having integrated switching, control, storage or amplification elements · CPC title