Microelectronic devices having air gap structures integrated with interconnect for reduced parasitic capacitances

Patent metadata

Field	Value
Publication number	US-12148690-B2
Application number	US-202318170754-A
Country	US
Kind code	B2
Filing date	Feb 17, 2023
Priority date	Dec 30, 2016
Publication date	Nov 19, 2024
Grant date	Nov 19, 2024

Abstract

Embodiments of the invention include a microelectronic device that includes a substrate, at least one dielectric layer on the substrate and a plurality of conductive lines within the at least one dielectric layer. The microelectronic device also includes an air gap structure that is located below two or more of the plurality of conductive lines.

First claim

The invention claimed is:

1. A method of fabricating an interconnect structure, the method comprising:
providing a substrate having a dielectric layer of dielectric material thereon;
forming at least one conductive layer having a plurality of conductive lines within the dielectric layer;
forming at least one feature with a depression in the dielectric material between two conductive lines;
depositing a group III Nitride layer within the depression such that the group III Nitride layer covers the bottom and sidewalls of the depression;
filling the depression with an oxide layer;
forming a group III Nitride layer on the oxide layer; and
etching the oxide layer at least partially to form at least one air gap structure integrated with the interconnect structure, the at least one air gap structure positioned between two adjacent conductive lines of the plurality of conductive lines.

2. The method of claim 1 , further comprising:
forming a metallization stack that includes first and second metal layers with the plurality of conductive lines being at the first metal layer of the metallization stack.

3. The method of claim 1 , wherein the group III Nitride layer comprises an Aluminum Nitride layer, a Boron Nitride layer, a Gallium Nitride layer, an Indium Nitride layer, or a combination of these layers.

4. The method of claim 1 , wherein the group III Nitride layer has a thickness of 50 to 250 nanometers.

5. The method of claim 1 , wherein the interconnect structure is disposed on the substrate to form a microelectronic device.

6. The method of claim 1 , wherein each air gap structure has a substantially rectangular shape or a substantially trapezoidal shape.

Assignees

• Tahoe Res Ltd

Inventors

• Then Han Wui
• Dasgupta Sansaptak
• Radosavljevic Marko
• Gardner Sanaz K

Classifications

• H10W20/072

  of dielectric parts comprising air gaps · CPC title

• H10W20/47

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title

• H10W20/46

  comprising air gaps · CPC title

• H10W10/021 Primary

  of air gaps · CPC title

• H10W10/20

  Air gaps · CPC title