Semiconductor structure and method for forming the same

Patent metadata

Field	Value
Publication number	US-12148657-B2
Application number	US-202318190328-A
Country	US
Kind code	B2
Filing date	Mar 27, 2023
Priority date	Apr 22, 2020
Publication date	Nov 19, 2024
Grant date	Nov 19, 2024

Abstract

A semiconductor interconnect structure includes a conductive line electrically coupled to an active semiconductor device, a first etch stop layer formed over the conductive line, a first dielectric layer formed over the first etch stop layer, a second etch stop layer formed over the first dielectric layer, a second dielectric layer formed over the second etch stop layer, and an interconnect structure electrically coupled to the via and extending through the first etch stop layer, the first dielectric layer, the second etch stop layer, and the second dielectric layer. The interconnect structure includes a via extending through the first etch stop layer, the second etch stop layer, and the first dielectric layer and a trench extending through the second dielectric layer.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
a via in contact with a conductive line and extending through a first etch stop layer, a first inter-metal dielectric layer, and a second etch stop layer, wherein the second etch stop layer is disposed over the first inter-metal dielectric layer, and the first inter-metal dielectric layer is disposed over the first etch stop layer; and
a trench in contact with the via and extending through an insulating layer and a second inter-metal dielectric layer, wherein the second inter-metal dielectric layer is disposed over the insulating layer which is disposed over the second etch stop layer;
wherein a junction of the via and the trench is aligned with an interface between the second etch stop layer and the insulating layer.

2. The semiconductor structure of claim 1 , wherein the second etch stop layer is disposed around the junction.

3. The semiconductor structure of claim 1 , wherein the insulating layer surrounds a lower portion of the trench.

4. The semiconductor structure of claim 1 , wherein a width of the via ranges from about 5 nanometers to about 15 nanometers.

5. The semiconductor structure of claim 1 , wherein a width of the trench ranges from about 15 nanometers to about 20 nanometers.

6. The semiconductor structure of claim 1 , wherein a thickness of the second etch stop layer ranges from about 10 angstroms to about 30 angstroms.

7. The semiconductor structure of claim 1 , wherein the via and trench are each formed of copper.

8. The semiconductor structure of claim 1 , wherein the first etch stop layer and the second etch stop layer each include at least one of: silicon nitride, silicon oxide, or silicon carbide.

9. The semiconductor structure of claim 1 , wherein a width of the trench is greater than a width of the via.

10. A method of fabricating a semiconductor structure, comprising:
forming an etch stop layer over a first inter-metal dielectric layer;
forming an insulating layer over the etch stop layer;
patterning the insulating layer to form a first opening partially extending through the insulating layer;
extending the first opening to extend through both the insulating layer and the etch stop layer;
forming a second inter-metal dielectric layer over the patterned insulating layer such that the second inter-metal dielectric layer extends through the first opening;
forming a second opening through at least the second inter-metal dielectric layer, the insulating layer, the etch stop layer, and the first inter-metal dielectric layer, wherein the second opening exposes a portion of a top surface of the etch stop layer; and
filling the second opening with a conductive material to form a first via and a first trench.

11. The method of claim 10 , wherein the step of forming a second opening comprises removing a portion of the insulating layer.

12. The method of claim 10 , wherein the first via is disposed under the first trench.

13. The method of claim 12 , wherein a width of the first via is less than a width of the first trench.

14. The method of claim 10 , further comprising:
patterning the insulating layer to form a third opening partially extending through the insulating layer, the third opening laterally spaced from the first opening;
extending the third opening to extend through both the insulating layer and the etch stop layer;
forming a fourth opening through at least the second inter-metal dielectric layer, the insulating layer, the etch stop layer, and the first inter-metal dielectric layer, wherein the fourth opening exposes another portion of the top surface of the etch stop layer and is laterally spaced from the second opening; and
filling the fourth opening with the conductive material to form a second via and a second trench.

15. The method of claim 14 , wherein the step of forming the third opening is performed concurrently with the step of forming the first opening, and the step of forming the fourth opening is performed concurrently with the step of forming the second opening.

16. The method of claim 14 , wherein the step of forming the third opening is performed subsequently to the step of forming the first opening, and the step of forming the fourth opening is performed concurrently with the step of forming the second opening.

17. The method of claim 14 , wherein the second via is disposed under the second trench, and a width of the second via is less than a width of the second trench.

18. The method of claim 14 , wherein a junction of the via and the trench is aligned with an interface between the etch stop layer and the insulating layer.

19. A method of fabricating a semiconductor structure, comprising:
forming an etch stop layer over a first inter-metal dielectric layer;
forming an insulating layer over the etch stop layer;
patterning the insulating layer to form a first opening partially extending through the insulating layer;
extending the first opening to extend through both the insulating layer and the etch stop layer;
forming a second inter-metal dielectric layer over the patterned insulating layer such that the second inter-metal dielectric layer fills the first opening;
forming a second opening through at least the second inter-metal dielectric layer, the insulating layer, the etch stop layer, and the first inter-metal dielectric layer, wherein the second opening exposes a portion of a top surface of the etch stop layer; and
filling the second opening with a conductive material to form a via and a trench, wherein a junction of the via and the trench is aligned with an interface between the etch stop layer and the insulating layer.

20. The method of claim 19 , wherein the step of forming a second opening comprises removing a portion of the insulating layer that overlaid the exposed portion of the top surface of the etch stop layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Chien-Han
• Chang Shih-Yu
• Chiu Chien-Chih
• Chen Yi-Tang
• Lin Da-Wei

Classifications

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/42 Primary

  Vias, e.g. via plugs · CPC title

• H10W20/47

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title