Random data generation circuit and read/write training circuit

Patent metadata

Field	Value
Publication number	US-12148504-B2
Application number	US-202318093728-A
Country	US
Kind code	B2
Filing date	Jan 5, 2023
Priority date	Jun 22, 2022
Publication date	Nov 19, 2024
Grant date	Nov 19, 2024

Abstract

A random data generation circuit includes: a first shift register and a second shift register. The first shift register includes n output ends Q 1 to Qn, the second shift register includes n output ends Qn+1 to Q 2 n , and each of the output ends outputs 1-bit data in a clock cycle of a clock signal; and a parallel-to-serial circuit, coupled to the output ends Q 1 to Q 2 n and configured to convert parallel data output from Q 1 to Q 2 n in a clock cycle into serial data for output. An initial value of the first shift register is different from an initial value of the second shift register. Data may be generated in parallel by using two shift registers, and the parallel data generated by the two shift registers is converted into serial data by using the parallel-to-serial circuit to be output.

First claim

What is claimed is:

1. A random data generation circuit, comprising:
a first shift register and a second shift register, configured to receive a same clock signal, wherein the first shift register comprises n output ends Q 1 to Qn, the second shift register comprises n output ends Qn+1 to Q 2 n , each of the output ends outputs 1-bit data in a clock cycle of the clock signal, and n is an integer greater than or equal to 1; and
a parallel-to-serial circuit, coupled to the output ends of the first shift register and the output ends of the second shift register and configured to convert parallel data output by the output ends Q 1 to Q 2 n in one clock cycle into serial data for output,
wherein an initial value of the first shift register is different from an initial value of the second shift register.

2. The random data generation circuit according to claim 1 , wherein the first shift register is the same as the second shift register.

3. The random data generation circuit according to claim 2 , wherein:
each of the first shift register and the second shift register comprises m triggers and m data processing circuits,
a data input end of each of the triggers is correspondingly connected to an output end of one data processing circuit,
a trigger input end of each of the triggers is configured to receive the clock signal,
each of the data processing circuits is configured to perform logical processing on output data of at least one trigger,
output ends of n triggers in the first shift register are respectively used as the n output ends of the first shift register,
output ends of n triggers in the second shift register are respectively used as the n output ends of the second shift register,
m is a positive integer greater than or equal to n, and
the initial value of the first shift register comprises an initial value of the data input ends of the triggers in the first shift register, and the initial value of the second shift register comprises an initial value of the data input ends of the triggers in the second shift register.

4. The random data generation circuit according to claim 3 , wherein m is 8 and n is 4.

5. The random data generation circuit according to claim 4 , wherein:
the eight triggers of the first shift register are successively denoted as a first trigger to an eighth trigger, the eight data processing circuits of the first shift register are successively denoted as a first data processing circuit to an eighth data processing circuit, and output ends of the first trigger to the fourth trigger are successively the output ends Q 1 to Q 4 ; and
the eight triggers of the second shift register are successively denoted as a ninth trigger to a sixteenth trigger, the eight data processing circuits of the second shift register are successively denoted as a ninth data processing circuit to a sixteenth data processing circuit, and output ends of the ninth trigger to the twelfth trigger are successively the output ends Q 5 to Q 8 .

6. The random data generation circuit according to claim 5 , wherein:
the first data processing circuit has three input ends, which are respectively connected to the output ends of the third trigger to the fifth trigger and configured to perform exclusive OR processing on input data received by the three input ends of the first data processing circuit; and
the ninth data processing circuit has three input ends, which are respectively connected to the output ends of the eleventh trigger to the thirteenth trigger and configured to perform exclusive OR processing on input data received by the three input ends of the ninth data processing circuit.

7. The random data generation circuit according to claim 5 , wherein:
the second data processing circuit has three input ends, which are respectively connected to the output ends of the fourth trigger to the sixth trigger and configured to perform exclusive OR processing on input data received by the three input ends of the second data processing circuit; and
the tenth data processing circuit has three input ends, which are respectively connected to the output ends of the twelfth trigger to the fourteenth trigger and configured to perform exclusive OR processing on input data received by the three input ends of the tenth data processing circuit.

8. The random data generation circuit according to claim 5 , wherein:
the third data processing circuit has four input ends, which are respectively connected to the output ends of the first trigger and the fifth trigger to the seventh trigger and configured to perform exclusive OR processing on input data received by the four input ends of the third data processing circuit; and
the eleventh data processing circuit has four input ends, which are respectively connected to the output ends of the ninth trigger and the thirteenth trigger to the fifteenth trigger and configured to perform exclusive OR processing on input data received by the four input ends of the eleventh data processing circuit.

9. The random data generation circuit according to claim 5 , wherein:
the fourth data processing circuit has four input ends, which are respectively connected to the output ends of the second trigger and the sixth trigger to the eighth trigger and configured to perform exclusive OR processing on input data received by the four input ends of the fourth data processing circuit; and
the twelfth data processing circuit has four input ends, which are respectively connected to the output ends of the tenth trigger and the fourteenth trigger to the sixteenth trigger and configured to perform exclusive OR processing on input data received by the four input ends of the twelfth data processing circuit.

10. The random data generation circuit according to claim 5 , wherein:
the fifth data processing circuit has four input ends, which are respectively connected to the output ends of the fourth trigger, the fifth trigger, the seventh trigger, and the eighth trigger and configured to perform exclusive OR processing on input data received by the four input ends of the fifth data processing circuit; and
the thirteenth data processing circuit has four input ends, which are respectively connected to the output ends of the twelfth trigger, the thirteenth trigger, the fifteenth trigger, and the sixteenth trigger and configured to perform exclusive OR processing on input data received by the four input ends of the thirteenth data processing circuit.

11. The random data generation circuit according to claim 5 , wherein:
the sixth data processing circuit has five input ends, which are respectively connected to the output ends of the first trigger, the third trigger, the fourth trigger, the sixth trigger, and the eighth trigger and configured to perform exclusive OR processing on input data received by the five input ends of the sixth data processing circuit; and
the fourteenth data processing circuit has five input ends, which are respectively connected to the output ends of the ninth trigger, the eleventh trigger, the twelfth trigger, the fourteenth trigger, and the sixteenth trigger and configured to perform exclusive OR processing on input data received by the five input ends of the fourteenth data processing circuit.

12. The random data generation circuit according to claim 5 , wherein:
the seventh data processing circuit has four input ends, which are respectively connected to the output ends of the first trigger to the third trigger and the seventh trigger and configured to perform exclusive OR processing on input data received by the four input ends of the seventh data processing circuit; and
the fifteenth data processing circuit has four input ends, which are re

Assignees

• Changxin Memory Tech Inc

Inventors

• Cheng Biao
• Lu Tianchen

Classifications

• G06F7/588

  Random number generators, i.e. based on natural stochastic processes · CPC title

• G11C7/222

  Clock generating, synchronizing or distributing circuits within memory device · CPC title

• H03K19/21 Primary

  EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical · CPC title

• G11C29/028

  with adaption or trimming of parameters · CPC title

• G11C29/10

  Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns · CPC title