Semiconductor device including multiple-input shift register circuit

Patent metadata

Field	Value
Publication number	US-10600493-B2
Application number	US-201816210823-A
Country	US
Kind code	B2
Filing date	Dec 5, 2018
Priority date	May 31, 2018
Publication date	Mar 24, 2020
Grant date	Mar 24, 2020

Abstract

A semiconductor device includes a mode control circuit suitable for selectively masking first and second initial input control signals and an initial feedback signal depending on a mode control signal and outputting first and second input control signals and a feedback signal; and a multiple-input shift register (MISR) circuit including a plurality of input selectors and a plurality of registers which are alternatively coupled in series with one another, wherein each of the plurality of input selectors combines an output signal of a previous stage register among the plurality of registers and an external input signal depending on the first and second input control signals and the feedback signal and provides an input signal for a next stage register among the plurality of registers.

First claim

What is claimed is:

1. A semiconductor device comprising:
a mode control circuit suitable for selectively masking first and second initial input control signals and an initial feedback signal depending on a mode control signal and outputting first and second input control signals and a feedback signal; and
a multiple-input shift register (MISR) circuit including a plurality of input selectors and a plurality of registers which are alternatively coupled in series with one another, wherein each of the plurality of input selectors combines an output signal of a previous stage register among the plurality of registers and an external input signal depending on the first and second input control signals and the feedback signal and provides an input signal for a next stage register among the plurality of registers.

2. The semiconductor device of claim 1 ,
wherein the mode control circuit outputs the first and second initial input control signals and the initial feedback signal as the first and second input control signals and the feedback signal, respectively, according to the mode control signal having a first logic level, and
wherein the mode control circuit outputs the first and second input control signals and the feedback signal by masking the first and second initial input control signals and the initial feedback signal to specific levels, respectively, according to the mode control signal having a second logic level.

3. The semiconductor device of claim 2 , wherein the mode control circuit activates and outputs the first input control signal and deactivates and outputs the second input control signal and the feedback signal based on the mode control signal having the second logic level.

4. The semiconductor device of claim 1 ,
wherein the mode control signal is at a first logic level when performing an MISR logical operation, and
wherein the mode control signal is at a second logic level when performing a read operation of reading out target data in the semiconductor device and outputting the target data to an external device.

5. The semiconductor device of claim 4 , wherein, when performing the read operation, an output signal of a last stage register among the plurality of registers is provided to the external device through a test input/output pad.

6. The semiconductor device of claim 1 , wherein an output signal of a last stage register among the plurality of registers is provided as the initial feedback signal.

7. The semiconductor device of claim 1 , wherein an input selector, which is positioned at a foremost stage of serial coupling, receives target data read in the semiconductor device as an output signal of a previous stage flip-flop.

8. The semiconductor device of claim 1 , wherein each of the plurality of input selectors selects a signal which is obtained by combining the feedback signal and an output signal of a previous stage register depending on the first input control signal, and selects the external input signal depending on the second input control signal.

9. The semiconductor device of claim 1 , wherein the mode control circuit comprises:
a first logic component suitable for performing an OR operation on the mode control signal and the first initial input control signal to output the first input control signal;
a second logic component suitable for performing an AND operation on an inverted mode control signal and the second initial input control signal to output the second input control signal; and
a third logic component suitable for performing an AND operation on the inverted mode control signal and the initial feedback signal to output the feedback signal.

10. The semiconductor device of claim 1 , wherein at least one of the plurality of input selectors comprises:
a first logic gate suitable for performing a NAND operation on the first input control signal and an output signal of a previous stage register;
a second logic gate suitable for performing a NAND operation on the second input control signal and the external input signal; and
a third logic gate suitable for performing an XOR operation on outputs of the first logic gate and the second logic gate to provide an input signal to a next stage register.

11. The semiconductor device of claim 1 , wherein at least one of the plurality of input selectors comprises:
a fourth logic gate suitable for performing an XOR operation on the feedback signal and an output signal of a previous stage register;
a fifth logic gate suitable for performing a NAND operation on an output of the fourth logic gate and the first input control signal;
a sixth logic gate suitable for performing a NAND operation on the second input control signal and the external input signal; and
a seventh logic gate suitable for performing an XOR operation on outputs of the fifth logic gate and the sixth logic gate to provide an input signal to a next stage register.

12. The semiconductor device of claim 1 , wherein the MISR circuit performs one of a reset function, a linear feedback shift register (LFSR) function, a register function and an MISR function, depending on the first and second input control signals.

13. A memory system, comprising:
a memory controller; and
a stack type memory device including a base die and a plurality of core dies which are stacked on the base die to transmit signals through a plurality of through-electrodes,
wherein the base die comprises:
a mode control circuit suitable for selectively masking first and second initial input control signals and an initial feedback signal depending on a mode control signal, and outputting first and second input control signals and a feedback signal; and
a multiple-input shift register (MISR) circuit including a plurality of input selectors and a plurality of registers which are alternatively coupled in series with one another, and suitable for selectively performing an MISR logical operation or a register read operation depending on the first and second input control signals and the feedback signal.

14. The memory system of claim 13 ,
wherein the mode control circuit outputs the first and second initial input control signals and the initial feedback signal as the first and second input control signals and the feedback signal, respectively, according to the mode control signal having a first logic level, and
wherein the mode control circuit outputs the first and second input control signals and the feedback signal by masking the first and second initial input control signals and the initial feedback signal to specific levels, respectively, according to the mode control signal having a second logic level.

15. The memory system of claim 14 , wherein the mode control circuit activates and outputs the first input control signal and deactivates and outputs the second input control signal and the feedback signal, based on the mode control signal having the second logic level.

16. The memory system of claim 13 , wherein the register read operation includes reading target data in the memory device.

17. The memory system of claim 13 , wherein, when performing the register read operation, the MISR circuit provides an output signal of a last stage register among the plurality of registers to the memory controller through a test input/output pad.

18. The memory system of claim 13 , wherein each of the plurality of input selectors combines an output signal of a previous stage register and an external input signal depending on the first and second input control signals and the feedback signal and provides an input signal of a next stage register amon

Assignees

• Sk Hynix Inc

Inventors

• Ku Young-Jun

Classifications

• G11C29/32 Primary

  Serial access; Scan testing · CPC title

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G11C19/14 Primary

  using magnetic elements in combination with active elements, e.g. discharge tubes, semiconductor elements {(contains no documents, see provisionally G11C19/02 - G11C19/10)} · CPC title

• G11C7/1069

  I/O lines read out arrangements · CPC title

• G11C19/287 Primary

  Organisation of a multiplicity of shift registers · CPC title